SRAM Backside Interconnect Layout for Lower Contact Parasitics
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Solution Overview
Problem
As integrated circuit technologies progress towards smaller technology nodes, the contact structures in SRAM cells face challenges in reducing resistance and capacitance, leading to high resistance and capacitance, which results in low drive current and slow speed due to tightly spaced frontside interconnects.
Innovation Solution
Incorporating both frontside and backside interconnects in SRAM devices, where sources of pull-down transistors are coupled to a backside ground rail through backside contacts, and omitting frontside contact structures to reduce resistance and capacitance, allowing for wider metal lines and greater spacing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If frontside interconnects are tightly spaced to increase routing density, then routing efficiency is improved, but resistance and capacitance increase leading to low drive current and slow speed
Solution Approach 1:
The patent introduces backside interconnects as a second dimensional layer for signal routing. By moving ground connections to the backside of the substrate, the design creates a three-dimensional interconnect architecture that separates frontside data lines from backside ground lines, effectively adding a spatial dimension to the routing solution and reducing parasitic effects on signal lines.
Solution Approach 2:
The interconnect architecture is segmented into frontside and backside components. Frontside metal lines carry data signals while backside metal lines carry ground references, dividing the interconnect function into separate spatial zones. This segmentation allows each layer to be optimized independently for its specific function.
2Reliability
If frontside contact structures are included to provide electrical connections, then electrical connectivity is ensured, but resistance and capacitance increase
Solution Approach 1:
The patent extracts the ground connection function from the frontside contact structures and relocates it to dedicated backside contact structures. By removing the ground connection requirement from frontside contacts, these contacts can be minimized to only the essential data signal connections, reducing their parasitic resistance and capacitance while maintaining electrical connectivity through the backside ground path.
3Power
If metal line width is increased to reduce resistance, then drive current is improved, but area occupied increases
Solution Approach 1:
The patent utilizes the vertical dimension by implementing ground connections on the backside of the substrate. This allows frontside metal lines to be narrower since they only need to carry data signals, while the ground return path is provided separately in the third dimension through backside contacts and ground lines, reducing the area requirement for high-current-carrying wide metal traces.
Data Source
AI summary
A semiconductor structure according to the present disclosure includes a backside metal line, a backside dielectric layer over the backside metal line, a first source/drain feature and a second source/drain feature over the backside dielectric layer, a first backside contact extending through the backside dielectric layer to couple to a bottom surface of the first source/drain feature, a second backside contact extending through the backside dielectric layer to couple to a bottom surface of the second source/drain feature, a dielectric layer disposed over the backside dielectric layer, the first source/drain feature and the second source/drain feature, a common contact extending through the dielectric layer to electrically couple to the first source/drain feature and the second source/drain feature, an etch stop layer disposed over and interfacing the dielectric layer and the common contact. The common contact is not electrically coupled to any conductive feature that extends through the etch stop layer.