SRAM Cell Layout Using Backside Load Contacts for Higher Density
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Solution Overview
Problem
Existing SRAM cells with multiple transistors face challenges in achieving compact size and high memory capacity due to large dimensions, which are exacerbated by the integration of multi-gate structures like FinFETs or GAA transistors.
Innovation Solution
The implementation of four-transistor-two-resistor (4T2R) and four-transistor-two-capacitor (4T2C) SRAM cells, where load resistors or capacitors are integrated into backside contacts, allowing the SRAM region to directly abut logic circuit regions, reducing cell dimensions by 15-30% and macro dimensions by over 50%.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multi-gate structures (FinFETs or GAA transistors) are integrated into SRAM cells to enhance performance, then device performance is improved, but cell dimensions increase
Solution Approach 1:
The patent merges the load resistor or capacitor functions directly into the backside contact structure. The backside contact serves dual purposes: providing electrical connection to the substrate and functioning as the load element. This integration eliminates the need for separate load components, thereby reducing cell area while maintaining the performance benefits of multi-gate transistor structures.
Solution Approach 2:
The patent utilizes the vertical dimension by implementing the load function in the backside contact layer, which is spatially separated from the main transistor circuit plane. This moves the load element to another dimension (the substrate interface), allowing the front-side transistor structures to be optimized for performance without area penalty from additional planar components.
2Ease of manufacture
If traditional SRAM cell layouts are used, then manufacturing is simpler, but integration efficiency is reduced and macro dimensions are larger
Solution Approach 1:
The backside contact is designed to simultaneously provide substrate connection and load function, merging two previously separate elements into one. This reduces the number of discrete components and interconnections required, thereby improving integration efficiency and reducing macro dimensions while maintaining manufacturing feasibility through standard backside contact processing.
Solution Approach 2:
The backside contact structure is given multiple functions: it serves as the electrical connection path to the substrate and simultaneously functions as the load resistor or capacitor. This multi-functionality eliminates the need for dedicated load components, improving integration density without complicating the manufacturing process, as the backside contact formation is a standard step in semiconductor fabrication.
Data Source
AI summary
A semiconductor device according to the present disclosure includes a first transistor and a second transistor sharing a first source/drain feature, a third transistor and a fourth transistor sharing a second source/drain feature, a first source/drain contact disposed over the first source/drain feature, a second source/drain contact disposed over the second source/drain feature, a first backside via disposed below the first source/drain feature, and a second backside via disposed below the second source/drain feature. A gate structure of the first transistor is coupled to the second source/drain contact and a gate structure of the fourth transistor is coupled to the first source/drain contact.