SRAM Backside Interconnect for Multi-Port Bitline Routing
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Solution Overview
Problem
Existing SRAM memory units face limitations in memory speed and power efficiency due to constrained bitline routing and mutual capacitance between gate structures and bitlines, which restricts the ability for simultaneous multi-port operations without increasing memory unit area.
Innovation Solution
The proposed SRAM memory unit design features a cell height twice that of existing units and a cell width halved, with backside interconnection of bitline pairs, enhancing routing flexibility and reducing mutual capacitance by moving bitlines to the backside, thus improving memory speed and power efficiency without increasing area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If bitline routing is constrained on the front side of the memory unit, then routing complexity is reduced, but mutual capacitance between gate structures and bitlines increases, degrading memory speed
Solution Approach 1:
The patent moves the bitline routing from the front side (2D plane) to the backside of the memory unit, utilizing the third dimension (depth/vertical layering) to resolve the conflict between routing complexity and mutual capacitance. This dimensional transition allows bitlines to be positioned away from gate structures, reducing capacitive coupling while maintaining routing simplicity through dedicated backside pathways.
Solution Approach 2:
The memory unit is segmented into front-side and back-side regions with distinct functional assignments. The front side houses gate structures and control circuits, while the backside is dedicated to bitline routing. This spatial segmentation isolates the bitlines from gate structures, eliminating mutual capacitance interference while organizing routing paths to reduce overall system complexity.
2Use of energy by moving object
If bitline width is increased to reduce resistance, then power efficiency improves, but mutual capacitance with gate structures increases, slowing down memory operations
Solution Approach 1:
By relocating bitlines to the backside of the memory unit, the patent enables increased bitline width without proximity to gate structures. This dimensional separation allows thicker bitlines that reduce resistive losses and improve power efficiency, while the increased spacing to gate structures simultaneously reduces mutual capacitance, preventing speed degradation.
Solution Approach 2:
The bitline geometry is optimized with locally varied properties: increased width and thickness in regions where spacing from gate structures permits, thereby reducing resistance and improving power efficiency. The local quality of bitline dimensions is adjusted based on the spatial relationship with gate structures, maximizing electrical performance without capacitive penalties.
3Productivity
If multiple port operations are implemented to increase throughput, then productivity improves, but routing complexity and mutual capacitance increase, degrading memory speed
Solution Approach 1:
The backside interconnection architecture provides dedicated routing dimensions for multiple port operations. Each port can utilize independent backside pathways for bitline access, allowing parallel multi-port operations without increasing front-side routing complexity or mutual capacitance. The additional spatial dimension enables simultaneous access paths that maintain signal integrity and speed.
Solution Approach 2:
The memory unit is segmented to support multiple independent access ports, each with dedicated bitline routing on the backside. This segmentation allows simultaneous multi-port operations where each port has its own routing infrastructure, preventing cross-talk and capacitance accumulation that would otherwise degrade speed, while achieving high throughput through parallel access.
Data Source
AI summary
A method includes receiving design data of a memory device; and generating a design layout including a first cell according to the design data. The first cell includes a first, a second, a third, and a fourth gate structures parallel to each other. The first cell further includes: a data storage element arranged including a first data node and a second data node, wherein the data storage element further comprises four transistors associated with the second and the third gate structures; a first access transistor and a second access transistor coupled to the first data node and the second data node, respectively; a first conductive line coupled to gate structures of the first access transistor and the second access transistor, respectively; and a second conductive line and a third conductive line each coupled to a source/drain region of the respective first and second access transistors.