SRAM Backside Bitline and Wordline Routing for Lower RC Delay
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Solution Overview
Problem
As standard cells become smaller, providing connections to components within the cells becomes more difficult, and resistances within the cells, such as in metal traces or interfaces between diffusion regions and metal traces, affect performance, making it challenging to improve circuit density and reduce resistances.
Innovation Solution
Utilizing backside metal layers for power and control signal connections in standard cells, providing redundant connections both above and below the transistors to reduce interface resistances and improve performance without increasing cell size or power.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If standard cell size is reduced to increase circuit density, then circuit density improves, but connection access to components becomes more difficult and interface resistances increase
Solution Approach 1:
The patent introduces backside metal layers (MB0, MB1) beneath the transistor substrate to provide additional connection pathways. This vertical dimension expansion allows connections to reach components without increasing horizontal cell area, thereby maintaining circuit density while improving connection accessibility.
Solution Approach 2:
The connection system is segmented into topside metal layers (MT0, MT1) and backside metal layers (MB0, MB1), with each layer serving specific routing functions. This segmentation distributes connection paths across multiple layers, reducing resistance at any single interface while maintaining high circuit density.
2Quantity of substance
If standard cell size is reduced to increase circuit density, then circuit density improves, but interface resistances increase and performance deteriorates
Solution Approach 1:
By adding backside metal layers beneath the substrate, the patent creates redundant connection paths that reduce interface resistances. This vertical routing approach maintains small cell footprint while improving electrical performance through multiple parallel connection pathways.
Solution Approach 2:
The patent changes the physical configuration of connection paths by introducing backside routing layers, effectively increasing the number of parallel conduction paths. This parameter change reduces overall interface resistance without altering the horizontal cell dimensions, thereby maintaining high circuit density.
3Reliability
If redundant connections are provided both above and below transistors to reduce interface resistances, then performance improves, but device complexity increases
Solution Approach 1:
The patent utilizes the vertical dimension by implementing backside metal layers (MB0, MB1) that route connections beneath the transistor substrate. This approach reduces interface resistances through redundant pathways without increasing horizontal complexity, as the additional connections are stacked vertically rather than spread out laterally.
Data Source
AI summary
Various implementations of backside and topside routing of bitlines and wordlines in memory arrays are disclosed. Bitlines in backside and topside metal layers may be alternated between adjacent bit cells in a memory array. Alternating the location of the bitlines between bit cells in the memory array may reduce bitline capacitance in a memory array. Placing wordlines in backside metal layers may allow dual wordlines to be implemented across a span of bit cells in a memory array. The dual wordlines may be alternately connected to adjacent bit cells, thereby allowing selective toggling of bit cells based on the wordline transmitting a control signal.