SRAM Backside Shared Contact Layout for Interconnect Congestion
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Solution Overview
Problem
The increasing demand for highly reliable, high-speed, and multi-functional semiconductor memory devices poses challenges in achieving efficient integration and complex structures, particularly in the manufacturing of static random access memory (SRAM) cells, where existing technologies struggle with effective electrical connections and reduced congestion in metal interconnection layers.
Innovation Solution
The semiconductor memory device incorporates a substrate with a shared contact that electrically connects the source/drain and gate electrodes, buried in the substrate, and a backside metal layer on the opposite surface, reducing congestion in the metal interconnection layers and improving electrical connections by merging backside active and gate contacts into a single shared contact.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate active contact and gate contact are formed on the backside of substrate, then electrical connection is achieved, but metal interconnection layers become congested and resistance increases
Solution Approach 1:
The patent merges the previously separate active contact and gate contact into a single shared contact structure formed on the backside of the substrate. This shared contact simultaneously electrically connects to both the active region and gate, eliminating the need for separate contact paths and thereby reducing metal interconnection layer congestion while maintaining reliable electrical connections.
2Reliability
If more metal interconnection layers are added to reduce congestion, then connection reliability improves, but manufacturing complexity and cost increase
Solution Approach 1:
The patent moves the contact formation to the backside of the substrate, utilizing the third dimension (vertical depth) to resolve horizontal congestion issues. By forming contacts on the opposite surface of the substrate, the design eliminates the need for additional metal interconnection layers, thereby maintaining connection reliability while reducing manufacturing complexity.
3Speed
If high-speed performance is achieved through complex structures, then processing speed improves, but manufacturing precision requirements increase
Solution Approach 1:
The patent inverts the conventional contact formation approach by creating contacts on the backside of the substrate rather than the front side. This inversion simplifies the overall structure and reduces the precision requirements for aligning multiple metal interconnection layers, while still achieving high-speed performance through reduced resistance and congestion.
Data Source
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AI summary
A semiconductor memory device includes a substrate including first and second surfaces opposite to each other, a first active pattern on the first surface, a first channel pattern on the first active pattern and a first source/drain pattern connected to the first channel pattern, a gate electrode provided on the first channel pattern and extending in a first direction, the gate electrode adjacent to the first source/drain pattern in a second direction intersecting the first direction, a shared contact provided under the first source/drain pattern and the gate electrode and electrically connecting the first source/drain pattern and the gate electrode to each other, and a backside metal layer on the second surface.