Granular SRAM Retention Control Using Ballast Drivers and LDOs
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Solution Overview
Problem
Existing solutions for managing retention voltages in digital logic circuits, such as SRAM memory arrays, are inefficient due to high leakage conditions caused by manufacturing variations, leading to over-design and inefficient power management.
Innovation Solution
Implementing a system with granular control over retention and active states of digital logic circuits using a plurality of voltage regulators and ballast drivers, allowing each memory array to be individually controlled through active signal switches, and employing low dropout regulators to minimize power dissipation and area usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If typical solutions for tracking and managing retention voltages are used, then power management is simplified, but leakage current increases due to high leakage conditions and manufacturing variations
Solution Approach 1:
The patent divides the memory array into multiple segments or blocks, each with independent retention voltage control. This allows selective placement of individual memory blocks into retention state based on actual usage patterns, minimizing leakage current from inactive blocks while maintaining simplicity through modular control architecture
Solution Approach 2:
The patent implements local retention voltage control where different voltage levels are applied to different memory blocks based on their specific retention needs. This localized approach reduces overall leakage current by applying retention voltage only where necessary, rather than uniformly across the entire memory array
2Loss of energy
If granular control over retention states is implemented for each digital circuit, then leakage current is reduced, but device complexity increases due to multiple voltage regulators and control circuits
Solution Approach 1:
The patent merges multiple retention voltage control functions into a unified control mechanism that manages multiple memory blocks simultaneously. By combining control logic and using shared reference circuits, the patent achieves granular control over individual memory blocks while reducing the overall complexity compared to fully independent control circuits for each block
Solution Approach 2:
The patent designs control circuits that can universally manage retention states across different memory blocks with varying sizes and access patterns. The control mechanism is multi-functional, handling both small and large memory blocks using the same architectural principles, thereby reducing complexity through standardized control approaches
3Loss of energy
If voltage is reduced during retention state, then leakage current is significantly reduced, but manufacturing variations require higher margins that reduce efficiency
Solution Approach 1:
The patent implements dynamic retention voltage adjustment where the voltage level is adaptively tuned based on actual retention requirements and manufacturing variations. Rather than using fixed conservative voltage margins, the system dynamically optimizes voltage levels to achieve adequate retention with minimal leakage, improving both reliability and energy efficiency
Solution Approach 2:
The patent changes the retention voltage parameter based on specific memory block characteristics and operational conditions. By adjusting voltage levels to match actual retention needs rather than applying uniform conservative margins, the patent reduces leakage current while maintaining adequate retention reliability across varying manufacturing conditions
4Area of stationary object
If low dropout regulators are used, then power dissipation and area usage are minimized, but control precision over retention voltage may be reduced
Solution Approach 1:
The patent introduces intermediary voltage reference circuits and buffer stages between the LDO regulators and the memory blocks. These intermediary elements act as mediators that amplify or extend the control capability of compact LDO circuits, maintaining voltage control precision while benefiting from the low power dissipation and small area characteristics of LDO technology
Data Source
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AI summary
Systems and devices are provided to enable granular control over a retention or active state of each of a plurality of memory circuits, such as a plurality of memory cell arrays, within a memory. Each respective memory array of the plurality of memory arrays is coupled to a respective ballast driver and a respective active memory signal switch for the respective memory array. One or more voltage regulators are coupled to a ballast driver gate node and to a bias node of at least one of the respective memory arrays. In operation, the respective active memory signal switch for a respective memory array causes the respective memory array to transition between an active state for the respective memory array and a retention state for the respective memory array.