SRAM Bank Deep Retention With Access-Aware Peripheral Power Gating
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Solution Overview
Problem
SRAM consumes significant static power even when not in use, particularly at lower geometries, due to changes in address and data pins, and existing designs fail to efficiently manage power in SRAM banks with varying access frequencies.
Innovation Solution
Implementing a power management apparatus with a power switch and isolation cell to gate power to memory peripherals and isolate data pins for seldom accessed SRAM banks, while maintaining the memory core powered, using power management circuitry to monitor access patterns and transition banks to deep retention mode.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If SRAM banks are kept powered on to retain data, then data retention is ensured, but static power consumption increases significantly
Solution Approach 1:
The SRAM is divided into multiple banks, each with independent power management. The power management circuitry can selectively power down individual banks based on access patterns, allowing data retention in active banks while reducing power consumption in inactive banks.
Solution Approach 2:
The patent changes the power state parameter of SRAM banks dynamically. By transitioning banks between active and deep retention modes based on access patterns, the system maintains data retention while optimizing power consumption.
2Use of energy by moving object
If power is gated to SRAM banks to reduce power consumption, then static power usage decreases, but access latency increases
Solution Approach 1:
The power management circuitry monitors access patterns and proactively transitions SRAM banks to deep retention mode before they are needed, and restores power in advance when access is anticipated. This preliminary action minimizes the impact on access latency while maintaining power savings.
Solution Approach 2:
The system dynamically adjusts the power state of SRAM banks based on real-time access patterns. The power management circuitry continuously monitors and adapts the power configuration, transitioning banks between active and deep retention modes as needed to balance power consumption and access performance.
3Speed
If all SRAM banks are kept accessible, then data access speed is maintained, but power consumption increases
Solution Approach 1:
The SRAM is segmented into multiple independently managed banks. The power management circuitry can selectively maintain high-speed access in frequently accessed banks while powering down seldom accessed banks, achieving both speed and power efficiency.
Solution Approach 2:
Different SRAM banks are assigned different power states based on their specific access patterns. Frequently accessed banks remain in active mode for high-speed access, while seldom accessed banks are placed in deep retention mode to reduce power consumption.
Data Source
AI summary
An apparatus for power management of a static random access memory (SRAM) bank is provided. The apparatus may include a memory core to store data, a memory peripheral connected to the memory core for supporting memory operations, a core power pin connected to a power source to supply power to the memory core, a peripheral power pin connected to the power source via a power switch, the power switch to selectively gate power to the memory peripheral, an isolation cell connected to one or more data pins of the SRAM bank, the isolation cell to isolate the data pins when the memory peripheral is powered down, and power management circuitry to monitor access patterns of the SRAM bank, determine how frequently the SRAM bank is accessed, and place the SRAM bank in deep retention mode by controlling the power switch and the isolation cell.