SRAM Bending Circuit for Low Voltage Self-Timer Delay
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Solution Overview
Problem
As integrated circuits are scaled down, the read and write margins of SRAM cells are reduced, leading to errors in operations due to the compromise between transistor strength for write and read operations, especially at lower voltages.
Innovation Solution
A bending circuit for SRAM self-timer that includes specific configurations of NFET and PFET transistors and a capacitor, allowing for increased self-timer delay at low voltage corners without significantly impacting high voltage corners, by charging a capacitor and transitioning output signals based on input signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If transistors are made weak to be over-driven during write operations, then write performance is improved, but read performance deteriorates because the transistors cannot maintain data value while driving bitline
Solution Approach 1:
The patent introduces a bending circuit that segments the read and write operations by adding intermediate control stages. The bending circuit includes multiple transistors (T1-T4) and a capacitor that create distinct operational paths, allowing the cross-coupled latch to be selectively over-driven during writes while maintaining stability during reads through controlled voltage transitions.
Solution Approach 2:
The bending circuit acts as an intermediary between the input signals and the cross-coupled latch. The additional transistors and capacitor in the bending circuit mediate the signal transitions, providing buffered control that prevents direct conflict between write over-driving and read stability requirements.
2Volume of moving object
If operation voltage is reduced to scale down integrated circuits, then device size is reduced, but read and write margins are reduced leading to operation errors
Solution Approach 1:
The bending circuit changes the voltage parameters dynamically during operation. The capacitor in the bending circuit stores and releases voltage to provide temporary voltage boosting during critical transitions, effectively increasing the operating margins without requiring a permanent increase in supply voltage, thus maintaining scalability while improving reliability.
3Speed
If access transistor on-resistance is reduced for write operations, then write speed is improved, but cell stability deteriorates due to increased coupling to bitline capacitance
Solution Approach 1:
The bending circuit introduces dynamic control of the access transistor operation. The additional transistors and capacitor create time-dependent control signals that temporarily modify the effective on-resistance during write operations, allowing low resistance for fast writes while maintaining high resistance for stability during reads through dynamic switching.
Data Source
AI summary
The present disclosure relates to a circuit, including a first transistor with a drain connected to a capacitor, a gate connected to an input of an inverter and a source connected to ground, a second transistor with a drain connected to the capacitor and a gate connected to the input of the inverter, a third transistor with a source connected to an output of the inverter, a drain connected to a source of the second transistor, and a gate connected to the input of the inverter, and a fourth transistor with a source connected to the source of the third transistor, a drain connected to ground, and a gate connected to the capacitor.