SRAM Memory Cell Biasing for Low Voltage Read Speed
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Solution Overview
Problem
SRAM memory cells face challenges in operating over a wide range of supply voltage values, particularly at low voltages, leading to increased reading time and timing faults due to variability in CMOS transistors, which existing solutions like redundancy and error correction codes are inadequate to address effectively.
Innovation Solution
The memory device adjusts the read current of SRAM cells by modulating the threshold voltage of transistors in the read port and P-type transistors through biasing, allowing for independent control of bias potentials across columns or groups of memory cells to optimize reading speed and power consumption, reducing timing faults without relying on redundancy or error correction codes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the supply voltage is reduced to improve power consumption, then energy efficiency is improved, but reading speed decreases and timing faults increase
Solution Approach 1:
The patent applies parameter changes by dynamically adjusting the threshold voltage of transistors in the read port through biasing mechanisms. By modifying the threshold voltage parameter, the patent compensates for the speed degradation caused by reduced supply voltage, allowing the memory cell to maintain adequate reading speed even at lower operating voltages, thus resolving the contradiction between power consumption and reading speed
Solution Approach 2:
The patent implements dynamics by introducing dynamic biasing control that adapts the transistor threshold voltages based on operating conditions. The biasing mechanism dynamically adjusts electrical parameters during operation to optimize performance across different voltage ranges, enabling the system to maintain timing accuracy and reading speed variability within acceptable limits despite voltage fluctuations
2Use of energy by moving object
If the supply voltage is reduced to improve power consumption, then energy efficiency is improved, but timing faults increase
Solution Approach 1:
The patent modifies electrical parameters by dynamically adjusting transistor threshold voltages through biasing, which compensates for timing degradation at low voltages. This parameter adjustment ensures that timing faults are reduced to below 10^-9 while maintaining low power consumption, resolving the contradiction between energy efficiency and reliability
Solution Approach 2:
The patent implements feedback mechanisms that monitor operating conditions and adjust biasing voltages accordingly. This feedback control ensures that timing accuracy is maintained within acceptable limits by dynamically compensating for voltage-induced timing variations, thereby reducing timing faults while preserving low-power operation
3Manufacturing precision
If FDSOI technology is used to reduce transistor dispersion, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
The patent applies local quality by implementing selective biasing of specific transistor groups (read port transistors versus other transistors) with different threshold voltage adjustments. This localized control approach optimizes performance for critical read operations while maintaining simplicity in other areas, balancing manufacturing precision improvement with device complexity management
Solution Approach 2:
The patent segments the transistor population into different groups with different biasing strategies. By dividing transistors into read port transistors and other transistors with distinct biasing requirements, the patent achieves precise control over critical timing parameters while keeping the overall device structure manageable, thus resolving the contradiction between manufacturing precision and device complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively compensates for the drop in reading speed caused by low supply voltage, reduces timing faults, and improves write performance and stability, enhancing the energy efficiency and performance of SRAM memory cells, especially in deca-nanometric CMOS technologies.
Implementation Method 1
The memory device adjusts the read current of SRAM cells by modulating the threshold voltage of transistors in the read port and P-type transistors through biasing
Data Source
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AI summary
Memory device (100) comprising: - an array of several columns of SRAM memory cells, each comprising transistors forming a memory point, a read port and a write port, and such that the transistors of the read port and/or the P-type transistors have a second cell (133) of a conductivity type opposite to that of a first cell (125) of the other transistors; - means (136, 138, 140, 142) for biasing the second cells, capable of selecting and applying bias values to the second cells, comprising: • a memory circuit for the bias states of the second cells for each column or group of columns; • a selection circuit applying a bias potential to the second cells according to one of the values received at the input, depending on the stored bias state associated with the column or group of columns.