SRAM Bias Controller for Read Write Voltage Optimization
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Solution Overview
Problem
As semiconductor technology scales to the 45 nm node and beyond, it becomes increasingly difficult to design SRAM cells that maintain balanced transistor strengths over varying temperature and bias conditions, leading to instability and performance tradeoffs between static noise margin (SNM), voltage transfer (Vtrip), and read current (Iread).
Innovation Solution
An SRAM array with a power supply controller that dynamically adjusts voltage levels, setting VDDM higher than VWL for read operations and VSSM to a lower level for write operations, while allowing VSSM to float after read operations, thereby optimizing SNM, Vtrip, and Iread by applying different bias conditions based on operation modes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If fixed voltage levels (Vdd and Vss) are used for SRAM operations, then circuit simplicity is maintained, but transistor strength balancing and performance optimization across different operations becomes difficult
Solution Approach 1:
The patent applies dynamics by transitioning from fixed voltage supplies to dynamic, operation-dependent voltage supplies. The power supply circuit now provides different voltage levels (Vdd1, Vdd2, Vss1, Vss2) based on whether the SRAM cell is in read or write mode, allowing optimal transistor biasing for each operation type while resolving the contradiction between circuit simplicity and performance optimization.
Solution Approach 2:
The patent changes the voltage parameters dynamically based on operation mode. By adjusting Vdd and Vss voltage levels according to whether read or write operations are performed, the system optimizes transistor strength balancing and performance without requiring complex manual intervention, thus resolving the contradiction between simplicity and reliability.
2Reliability
If different voltage levels are applied for read and write operations, then SNM and performance are improved, but power supply circuit complexity increases
Solution Approach 1:
The power supply circuit is designed with multi-functionality to handle both read and write operations with different voltage requirements. By integrating voltage selection logic that automatically provides appropriate voltage levels based on operation mode, the circuit achieves universal functionality without proportionally increasing complexity, thus resolving the contradiction between improved SNM and circuit complexity.
3Reliability
If VDDM is set higher than VWL for read operations, then SNM is improved, but power consumption increases
Solution Approach 1:
The system applies periodic action by switching voltage levels based on operation mode. During read operations, VDDM is temporarily raised above VWL to improve SNM, then returned to normal levels. This time-limited voltage boosting achieves the desired SNM improvement while minimizing overall power consumption, resolving the contradiction between reliability and energy usage.
Data Source
AI summary
An integrated circuit includes a SRAM array including a plurality of SRAM cells arranged in a plurality of rows and columns and having a plurality of word lines and bit lines for accessing rows and columns of cells. A power supply controller has an input operable for receiving an operation signal indicative of whether the array is in a read or write operation. The power supply controller is operable to provide a variable low voltage for the array (VSSM) coupled to a low voltage supply terminal of the array. A level of the VSSM is based on the operation signal, wherein VSSM is at a lower level when in the read operation than when in the write operation. A high voltage supply for said array (VDDM) coupled to a high voltage supply terminal for the array is biased above a word line voltage (VWL) level in the read operation.