SRAM Bias Circuit for Low Voltage Power Reduction
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Solution Overview
Problem
Existing SRAM circuits face challenges in reducing power consumption while maintaining data integrity, as lowering supply voltage below a certain threshold can cause transistor state flipping, leading to data loss, and current methods require higher voltages on-chip to achieve leakage reduction.
Innovation Solution
The SRAM facility operates by adjusting substrate and well biases using multiple voltage modes, allowing for lower supply voltages without compromising data integrity, achieved through a bias circuit responsive to digital control values and process state registers, which dynamically adjust voltages based on the SRAM cell's process corner and operating mode.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If supply voltage is lowered to reduce power consumption, then power consumption is reduced, but transistor state flipping occurs leading to data loss
Solution Approach 1:
The patent applies parameter changes by dynamically adjusting substrate bias voltage and well bias voltage independently of the supply voltage. This allows the SRAM cell to maintain stable transistor states at lower supply voltages by compensating for voltage threshold effects through bias adjustment, thereby preventing state flipping while enabling reduced power consumption
Solution Approach 2:
The invention implements dynamic bias adjustment where substrate and well biases are dynamically modified based on operating conditions and process variations. This dynamic control enables the circuit to adapt to changing conditions and maintain data integrity across different voltage levels, resolving the contradiction between low voltage operation and reliable data storage
2Loss of energy
If higher voltages are applied on-chip to reduce leakage, then leakage reduction is achieved, but power consumption increases
Solution Approach 1:
The patent applies local quality by independently controlling the bias conditions of specific transistor regions through separate substrate and well bias circuits. This localized bias control allows leakage reduction in specific areas without requiring global voltage increases, thereby reducing leakage while avoiding the associated power consumption penalty
Solution Approach 2:
The invention introduces bias circuits as intermediary elements that mediate between the supply voltage and the transistor operations. These intermediary bias circuits enable precise control of threshold voltages and leakage currents without directly increasing the supply voltage, thus achieving leakage reduction without proportional power consumption increase
Data Source
AI summary
An SRAM circuit that includes a biasing circuit adapted to selectively bias the transistors of the SRAM array to lower the threshold voltage of selected transistors. The SRAM circuit includes well voltages and positive voltages that are selectively different, and substrate voltages and ground voltages that are selectively different.