Segmented SRAM BIST Circuit Multiplexing for Read Path Testing
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Solution Overview
Problem
Conventional built-in self test (BIST) and automated test pattern generation (ATPG) techniques are insufficient for thoroughly testing the read circuitry of segmented static random access memory (SRAM) arrays, particularly in mission-critical applications where continuous and periodic testing is required.
Innovation Solution
The implementation of a memory circuit with enhanced BIST and ATPG capabilities, including multiple selectable data paths through multiplexing functions, sensing circuitry, latch circuits, and buffer circuits, allows for comprehensive testing of the read circuitry, including previously untestable sensing circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional BIST and ATPG techniques are used for testing segmented SRAM arrays, then the testing process is simple and quick, but the testing coverage is insufficient and cannot thoroughly test the read circuitry including sensing circuits
Solution Approach 1:
The memory array is divided into multiple sub-arrays, each with its own dedicated sensing circuit and data path. The row decoder is segmented to independently select word lines in different sub-arrays. This segmentation allows the BIST circuit to test each sub-array and its associated sensing circuit separately, achieving complete coverage of previously untestable components without requiring a single complex test path that would be difficult to design and verify.
Solution Approach 2:
Multiplexer circuits are introduced as intermediary components to selectively connect different data paths (including previously untestable sensing circuits) to the BIST comparison logic. These multiplexers act as mediators that enable the test controller to route test data through specific sub-array data paths based on test requirements, allowing comprehensive testing without permanently coupling all circuits together.
2Reliability
If multiple selectable data paths through multiplexing functions are implemented, then complete testing of read circuitry including sensing circuits is enabled, but the device complexity increases
Solution Approach 1:
The multiplexer circuits are designed to serve multiple functions: during normal operation they route data from memory cells to output, and during BIST operation they route test data through selected sub-array data paths to the comparison logic. The row decoder also serves dual purposes by enabling both conventional single-word-line selection and the new multi-word-line simultaneous selection mode. This multi-functionality reduces the need for separate dedicated test circuits, thereby limiting the increase in overall device complexity.
3Reliability
If simultaneous actuation of one word line per sub-array is enabled, then complete coverage of memory cells and sensing circuits is achieved, but the control circuit complexity increases
Solution Approach 1:
The row decoder is designed with dynamic control capabilities that allow it to switch between different operating modes: conventional mode where only one word line is actuated across the entire array, and BIST mode where one word line per sub-array is simultaneously actuated. The decoder's control logic dynamically adjusts its behavior based on the test mode signal, enabling flexible adaptation to different testing requirements without requiring hardware changes.
4Reliability
If conventional testing methods are used, then the test circuit is simple, but continuous and periodic testing required for mission-critical applications cannot be performed
Solution Approach 1:
The BIST circuit is designed to be self-contained and self-executing within the memory device. The test controller generates test patterns, routes them through the memory array and sensing circuits via the multiplexer data paths, captures the output, and performs comparison logic operations all internally without requiring external test equipment. This self-service capability enables continuous and periodic testing in mission-critical applications, as the memory can autonomously perform verification of its own functionality at any time.
Data Source
AI summary
The memory array of a memory includes sub-arrays with memory cells arranged in a row-column matrix where each row includes a word line and each sub-array column includes a local bit line. A row decoder circuit supports two modes of memory circuit operation: a first mode where only one word line in the memory array is actuated during a memory read and a second mode where one word line per sub-array are simultaneously actuated during the memory read. An input/output circuit for each column includes inputs to the local bit lines of the sub-arrays, a column data output coupled to the bit line inputs, and a sub-array data output coupled to each bit line input. Both BIST and ATPG testing of the input/output circuit are supported. For BIST testing, multiple data paths between the bit line inputs and the column data output are selectively controlled to provide complete circuit testing.