SRAM Bit Cell Layout via Asymmetric Double Patterning
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Solution Overview
Problem
The challenge in fabricating miniaturized SRAM bit cells lies in the difficulties of lithographic processes, particularly in patterning smaller technology nodes, where local interconnection layers are required, increasing manufacturing costs and time, and making it hard to achieve reliable printing of compact metal layers due to close spacing.
Innovation Solution
Implementing a double patterning lithography process that creates asymmetrically colored M1 layer structures, avoiding same-color tip-to-tip placements to improve printability and manufacturability, and forming bit cells without local interconnection layers, allowing for efficient and reliable printing of compact bit cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If single patterning lithography process is used to pattern metal layers, then manufacturing process is simpler and faster, but metal structures cannot be printed reliably when spacing is below 90 nm pitch
Solution Approach 1:
The patent divides the metal layer patterning into two separate steps: first patterning for initial metal structures, and second patterning for additional metal structures. This segmentation allows each patterning step to work within achievable precision limits while collectively achieving the overall compact layout that would be impossible with single patterning.
Solution Approach 2:
The first patterning step creates preliminary metal structures (such as word lines and bit lines) that serve as a foundation. Subsequent second patterning step adds remaining metal structures (such as ground lines and power lines) that would be impossible to create with single patterning due to spacing constraints.
2Area of stationary object
If local interconnection layers are added to achieve compact metal layer spacing, then bit cell area is reduced, but manufacturing complexity and cost increase
Solution Approach 1:
Instead of adding local interconnection layers (vertical dimension complexity), the patent resolves spacing issues by using two separate patterning steps (process dimension). This allows compact horizontal spacing of metal structures without introducing additional interconnection layers, maintaining manufacturing simplicity while achieving area reduction.
Solution Approach 2:
The first patterning step preliminarily establishes the main signal paths (word lines, bit lines) with sufficient spacing. The second patterning step then adds ground and power lines in the remaining spaces, achieving compact overall layout without requiring local interconnection layers that would add manufacturing complexity.
3Shape
If same-color tip-to-tip placement is used in M1 layer structures, then layout symmetry is maintained, but lithographic printability deteriorates
Solution Approach 1:
The patent intentionally introduces asymmetry in the placement of same-color tip edges by using offset distances between first and second patterning structures. This asymmetric arrangement ensures that tip-to-tip spacing between same-color structures exceeds minimum lithographic requirements, improving printability while maintaining overall layout functionality through the systematic use of first and second patterning layers.
Data Source
AI summary
An approach for providing SRAM bit cells with miniaturized bit cells, without local interconnection layers, with improved lithographic printability, and enabling methodology are disclosed. Embodiments include providing first color structures, in a M1 layer, including a first word line, a first bit line, a second bit line, a first ground line, a second ground line, a second latch line or a combination thereof, wherein the first color structures include side edges longer than tip edges; providing second color structures, in the M1 layer, including a second word line, a first power line, a second power line, a first latch line or a combination thereof, wherein the second color structures include side edges longer than tip edges; and forming a bit cell including the first color structures and the second color structures, wherein adjacent tip edges include a first color structure tip edge and a second color structure tip edge.