SRAM Bit Cell Layout for Simultaneous Read-Write Speed
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Solution Overview
Problem
Conventional dual-port SRAMs face issues with reduced operation speed due to increased resistance in word lines and variations in static noise margin, primarily caused by the adjacent positioning of transmission transistors and bit lines, which also limits simultaneous writing and reading capabilities.
Innovation Solution
The semiconductor memory device reconfigures the layout by isolating diffusion layers of transistors and optimizing the arrangement of word lines and bit lines, reducing the aspect ratio of bit cells and enhancing the isolation between transmission transistors, thereby reducing word line resistance and improving the static noise margin, allowing for simultaneous writing and reading.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If transmission transistors for different ports are positioned adjacent to each other in the horizontal direction, then the bit cell width becomes thinner, but the word line resistance rises and operation speed is reduced
Solution Approach 1:
The patent changes the arrangement dimension of transmission transistors from horizontal to vertical direction. Specifically, transmission transistors for different ports are positioned adjacent to each other in the vertical direction rather than horizontal direction, which maintains thin bit cell width while shortening word line length and reducing resistance, thus improving operation speed.
2Area of stationary object
If transmission transistors for different ports are positioned adjacent to each other in the horizontal direction, then the layout is compact, but the parity of bit lines is lost and static noise margin varies
Solution Approach 1:
The patent positions transmission transistors for different ports adjacent to each other in the vertical direction. This arrangement maintains bit line parity between ports and reduces variation in static noise margin, while still achieving compact bit cell area through optimized spatial configuration.
3Device complexity
If only two word lines are distributed in each bit cell, then the structure is simple, but simultaneous writing and reading with two read ports is not possible
Solution Approach 1:
The patent distributes four word lines (WL0, WL1, WL2, WL3) in each bit cell to enable multi-functional access. This configuration allows simultaneous writing and reading operations with two read ports, providing universal access capability while maintaining reasonable structural complexity through systematic word line arrangement.
Data Source
AI summary
A semiconductor memory device includes first and second driving transistors; first and second load transistors; and first and second transmission transistors. Their respective drain diffusion layers of the transistors are isolated from one another. The semiconductor memory device also includes a bit cell in which the first and second driving transistors, the first and second load transistors, and the first and second transmission transistors are arranged; a first wiring for connecting their respective drains of the first driving transistor, the first load transistor, and the first transmission transistor; and a second wiring for connecting their respective drains of the second driving transistor, the second load transistor, and the second transmission transistor.