SRAM Bit Cell Redundancy via Second Pass-Gate Transistor
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Data processing devices, such as memory devices, face failures due to variations in transistor electrical characteristics, leading to performance issues, which are often mitigated by redundant structures that increase costs and physical area.
Innovation Solution
A static random access memory (SRAM) system that reconfigures bit cells during manufacturing by using a second pass-gate transistor to support read operations, with fuse-programming to permanently switch to the second bit line if the desired access speed is achieved, ensuring both transistors' threshold voltages remain within permissible sigma variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If redundant structures are added to reduce the likelihood of memory device failure, then reliability is improved, but device area and cost increase
Solution Approach 1:
The patent applies preliminary action by testing each bit cell during manufacturing to identify weak transistors before the device is shipped. The system proactively detects threshold voltage variations and reconfigures affected bit cells using their second pass-gate transistors, preventing failures before they occur in normal operation. This eliminates the need for redundant structures while maintaining reliability.
Solution Approach 2:
The patent changes the operational parameters of bit cells by switching between different bit lines based on transistor performance. When a first pass-gate transistor is identified as weak, the system reconfigures the bit cell to use the second bit line and second pass-gate transistor for read operations. This parameter change allows marginal transistors to function adequately without requiring redundancy.
2Reliability
If redundant structures are added to compensate for defective portions, then reliability is improved, but manufacturing cost increases
Solution Approach 1:
The patent implements self-service by enabling the memory device to test and reconfigure itself during manufacturing. The system automatically identifies bit cells with weak transistors and performs self-reconfiguration by switching to alternative bit lines, eliminating the need for external intervention or complex testing equipment. This self-service approach reduces manufacturing complexity and cost while maintaining high reliability.
Solution Approach 2:
The patent performs preliminary testing and reconfiguration during the manufacturing process itself, before the device is shipped to customers. By identifying and correcting weak transistor issues proactively during fabrication, the system eliminates the need for costly post-manufacturing repairs or redundant structures, thereby reducing overall manufacturing cost while improving reliability.
3Ease of manufacture
If the threshold voltage variation tolerance is increased, then manufacturing ease is improved, but device performance deteriorates
Solution Approach 1:
The patent changes the operational parameters of individual bit cells based on their specific transistor characteristics. Instead of requiring all transistors to meet strict threshold voltage tolerances, the system measures each transistor's actual performance and reconfigures affected bit cells to use alternative bit lines. This allows the manufacturing process to have broader tolerance ranges while maintaining optimal performance through post-manufacturing optimization.
Solution Approach 2:
The patent performs preliminary measurement and characterization of transistor parameters during manufacturing, identifying which bit cells have transistors that fall outside the standard tolerance range. By detecting these variations early and reconfiguring the affected bit cells before the device is shipped, the system allows relaxed manufacturing tolerances while ensuring that each bit cell operates at its optimal performance level.
Data Source
AI summary
A device includes a memory configured so that, in the event that one pass-gate transistor associated with a bit cell is determined to be excessively weak such that reading the bit cell could be undesirably difficult, a second pass-gate transistor can be configured to support a read operation. For example, during a manufacturing test procedure, the access speed of each bit cell at a memory device is determined. If a bit cell fails to achieve a desired access speed, the column of the memory that includes the defective bit cell can be configured to access information stored at the bit cell using the second bit line associated with the second pass-gate transistor.