Self-Timed Bit Line Boost Circuit for SRAM Write Stability
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Solution Overview
Problem
Static random access memories (SRAMs) face challenges in maintaining stability during write operations due to process variations and power supply fluctuations, which can cause unintended changes in logic states, and require precise timing for voltage changes to ensure effective writing without impacting cycle time.
Innovation Solution
A self-timed bit line boost circuit that detects when a bit line is pulled low during a write operation and boosts the bit line voltage below ground level, using a detection circuit and capacitors to ensure reliable writing, independent of the bit line's ramp rate, thereby improving write performance and stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the power supply voltage is lowered for write operations to improve write performance, then write capability is improved, but precise timing is required which increases operational complexity and may impact cycle time
Solution Approach 1:
The detection circuit automatically detects when the bit line voltage reaches the predetermined level and autonomously triggers the boost circuit activation. This self-service mechanism eliminates the need for external timing control signals, allowing the circuit to self-regulate the voltage boosting timing based on actual bit line conditions, thereby improving write capability without increasing operational complexity
Solution Approach 2:
The detection circuit continuously monitors the bit line voltage and provides feedback to the boost circuit control logic. When the voltage reaches the predetermined threshold, the feedback signal triggers the boost circuit to activate. This feedback mechanism ensures precise timing control is achieved through actual voltage conditions rather than predetermined timing signals, resolving the contradiction between improved write capability and reduced operational complexity
2Reliability
If the power supply voltage is changed too early or too late to achieve effective writing, then write effectiveness is compromised, but adjusting timing precisely increases operational complexity
Solution Approach 1:
The patent replaces the mechanical/timing-based voltage change control system with an electric field-based detection and control system. The detection circuit uses electrical field sensing to monitor bit line voltage and automatically triggers voltage boosting when the predetermined level is reached, eliminating the need for complex external timing control while ensuring write effectiveness
Solution Approach 2:
The voltage boosting timing is determined by the bit line's own voltage state rather than external timing signals. The detection circuit senses when the bit line naturally reaches the predetermined voltage level and autonomously triggers the boost circuit, allowing the system to self-regulate timing based on actual operational conditions, thereby ensuring write effectiveness without increasing operational complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The self-timed bit line boost circuit ensures that memory cells are reliably written by boosting the bit line voltage at the correct time, enhancing write margin and stability, particularly for cells affected by process variations, without increasing cycle time or harming read operations.
Implementation Method 1
The capacitor is coupled to boost the bit line voltage below ground in response to a boost signal
Data Source
AI summary
A memory has an array of memory cells, column logic, a write driver, a voltage detector, and a bootstrap circuit. The array of memory cells is coupled to pairs of bit lines and word lines. The column logic is coupled to the array and is for coupling a selected pair of bit lines to a pair of data lines. The write driver is coupled to the pair of data lines. The voltage detector provides an initiate boost signal when a voltage of a first data line of the pair of data lines drops below a first level during the writing of the pair of data lines by the write driver. The bootstrap circuit reduces the voltage of the first data line in response to the boost enable signal. This is particularly beneficial when the number of memory cells on a bit line can vary significantly as in a compiler.