SRAM Bit Line Capacitance Adjustment for Accurate Defect Detection
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Solution Overview
Problem
In compiled SRAMs, the use of fixed capacitance for testing memory cells is ineffective due to variable bit line lengths, leading to inaccurate detection of memory cells with desired characteristics, as it can result in either excessive or insufficient charge accumulation, causing potential errors in determining the operation margin of memory cells.
Innovation Solution
A semiconductor device that includes a memory cell with a bit line pair changing voltage based on data, and a specifying circuit that couples a capacitative element to the bit line to set its voltage between specific voltages during testing, allowing for accurate detection of defective memory cells by adjusting the capacitance value according to bit line length variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If fixed capacitance is coupled to the bit line for testing, then it is possible to make the potential of the bit line constant in DRAM, but in compiled SRAM with variable bit line lengths, it causes excessive or insufficient charge accumulation leading to inaccurate detection
Solution Approach 1:
The patent applies the dynamics principle by making the capacitance value adjustable rather than fixed. The testing circuit includes a capacitance selection mechanism that allows the capacitance coupled to the bit line to be dynamically changed based on the bit line length. This enables the system to adapt to different bit line lengths in compiled SRAM while maintaining accurate charge redistribution and potential difference for reliable memory cell detection.
2Ease of manufacture
If the same fixed capacitance is coupled among SRAMs with different bit line lengths, then the structure is simple, but charge redistribution becomes inaccurate causing false detection of memory cells
Solution Approach 1:
The patent applies the parameter changes principle by varying the capacitance value parameter according to the bit line length. Different capacitance values are selected and coupled to bit lines of different lengths to ensure proper charge redistribution. This parameter adjustment maintains both the reliability of memory cell detection and reasonable structural simplicity by using a standardized testing circuit design with selectable capacitance values.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables precise detection of defective memory cells by ensuring the correct charge redistribution and potential difference across bit lines, reducing errors in determining the operation margin of memory cells, even in SRAMs with varying bit line lengths.
Implementation Method 1
a first capacitance is coupled between the bit line and a first potential in a first operation mode and a second capacitance is coupled between the bit line and a second potential in a second operation mode
Data Source
AI summary
A semiconductor device including an SRAM capable of sensing a defective memory cell that does not satisfy desired characteristics is provided. The semiconductor device includes a memory cell, a bit line pair being coupled to the memory cell and having a voltage changed towards a power-supply voltage and a ground voltage in accordance with data of the memory cell in a read mode, and a specifying circuit for specifying a bit line out of the bit line pair. In the semiconductor device, a wiring capacitance is coupled to the bit line specified by the specifying circuit and a voltage of the specified bit line is set to a voltage between a power voltage and a ground voltage in a test mode.