SRAM Bit Line Charge Recycling via Capacitive Clamping
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Solution Overview
Problem
Static random access memory (SRAM) faces challenges in improving operation margins and reducing power consumption in assist circuits, particularly due to the limitations of conventional assist circuit techniques that often compromise stability and performance by generating over-driven or under-driven voltages, leading to increased power consumption and stability issues in dense SRAM configurations.
Innovation Solution
The proposed SRAM design incorporates a pre-charge unit, a capacitor, and a clamping unit within a unit memory cell, which enables charge recycling by selectively connecting bit lines with the capacitor to adjust voltage levels, allowing for improved operation margins during reading and writing operations while reducing power consumption through a capacitive coupling effect.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional assist circuit techniques are used to improve operation margins, then reading and writing stability is improved, but power consumption increases significantly
Solution Approach 1:
The capacitor stores charge from the bit lines during precharge, recovering energy that would otherwise be wasted. This stored charge is then reused to assist the read and write operations, reducing the need for additional power consumption from external power supply circuits.
Solution Approach 2:
The capacitor serves the dual function of both precharging the bit lines and providing assist voltage during read/write operations. The circuit uses its own stored charge to improve operation margins without requiring separate power-consuming assist circuits.
2Reliability
If voltage levels are adjusted through conventional assist circuits to improve operation margins, then reading and writing stability is improved, but voltage control complexity increases
Solution Approach 1:
The capacitor performs multiple functions: precharging the bit lines, storing charge for assist operations, and providing voltage control during both read and write operations. This multi-functionality eliminates the need for separate voltage control circuits, reducing overall system complexity.
Solution Approach 2:
The precharge function and assist function are merged into a single capacitor component. Instead of having separate circuits for precharging and for improving operation margins, the same capacitor serves both purposes, simplifying the voltage control architecture.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the operation margins of both reading and writing operations without significant power consumption, enabling low-voltage operation without errors and allowing for seamless integration in both single-port and multi-port SRAM configurations without affecting other bit cells.
Implementation Method 1
allowing for improved operation margins during reading and writing operations while reducing power consumption through a capacitive coupling effect
Data Source
AI summary
A static random access memory comprises a pre-charge unit that supplies a pre-charge voltage to first and second bit lines connected to a bit cell; a capacitor, of which one or the other terminal is selectively connected to a ground terminal; a clamping unit that selectively connects the bit lines with the capacitor to adjust a voltage level of the bit lines; and a mux unit that is included in a unit memory cell including the bit cell, the pre-charge unit, the capacitor and the clamping unit, and activates the bit lines of the unit memory cell in response to reception of a selection signal; wherein the clamping unit connects the first and second bit lines with the capacitor in response to a charge sharing control signal, to induce charge sharing between the first and second bit lines and the capacitor.