SRAM Bit Line Potential Control for Write Reliability
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Solution Overview
Problem
In deep sub-micron SRAM cell manufacturing, instability and write/read failures occur due to statistical deviations, limiting the use of low voltage technologies and making it difficult to reliably write data, especially when the potential at the memory cell exceeds a certain threshold.
Innovation Solution
A potential controller is used to reduce the bit line potential below VSS during the write operation, compensating for statistical voltage variations and allowing for reliable writing of both '0' and '1' values without requiring additional power sources, by generating a third potential that is undershot or overshot relative to the standard potentials, thereby mitigating the influence of voltage fluctuations across access transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If low voltage technology (VDD=0.75V) is used for memory cells, then power consumption is reduced, but write reliability deteriorates due to statistical voltage variations exceeding the threshold
Solution Approach 1:
The bit line potential is pre-reduced below VSS (first potential) before the write operation to counteract the statistical positive voltage variations that will occur during writing. This preliminary anti-action ensures that even when voltage variations add to the bit line potential, the cell can still flip completely without write errors, thereby maintaining write reliability while using low voltage technology.
Solution Approach 2:
The invention changes the bit line potential parameter from the standard VSS level to a reduced level (third potential < VSS) during write operations. This parameter change compensates for manufacturing deviations and threshold voltage variations, enabling reliable writing in low voltage SRAM cells without requiring additional power sources or complex circuitry.
2Reliability
If the bit line potential is reduced below VSS during write operation, then write reliability is improved, but device complexity increases due to the need for additional potential control
Solution Approach 1:
The potential controller is integrated within the existing memory periphery and uses the same power supply voltages (VDD and VSS) already present in the system. It self-generates the reduced bit line potential (third potential) during write operations without requiring external power sources or additional complex control circuits, thereby improving write reliability while minimizing increases in device complexity.
3Reliability
If manufacturing deviations are addressed by designing memory periphery for each bit cell, then write reliability is improved, but area occupation and cost increase
Solution Approach 1:
The potential controller is designed as a universal component that can serve multiple bit cells during write operations. Instead of implementing individual compensation circuits for each bit cell, the shared potential controller applies the reduced bit line potential to any selected cell, thereby improving write reliability across all cells while minimizing the area occupied by memory periphery.
Data Source
AI summary
Method and memory device for reliably writing an information value to a memory element of the memory device. A first information value is represented by a first potential and a second information value is represented by a second potential. A bit line is provided for writing either the first information value or the second information value to the memory element. A potential controller is coupled to the bit line, where the potential controller is configured to apply a third potential to the bit line, which is less than the first potential when writing the first information value to the memory element.