SRAM Bit Line Pre-Charge Circuit for Uniform Voltage
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Solution Overview
Problem
Current SRAM memory devices face challenges in achieving high-speed read operations due to limitations in bit line pre-charging efficiency, which affects overall performance and speed.
Innovation Solution
The implementation of a pre-charge assist circuit that facilitates faster and more uniform pre-charging of bit lines by connecting both ends of the bit line pairs to the supply voltage, complementing the existing pre-charge circuit's efforts to ensure simultaneous and rapid voltage levels across the bit lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a conventional pre-charge circuit is used to charge bit lines, then the bit lines can be pre-charged to supply voltage, but the pre-charging speed is limited and uniformity across the bit line pair is poor
Solution Approach 1:
The pre-charge function is segmented into two independent circuits: a conventional pre-charge circuit connected to a first end of the bit line pair, and a pre-charge assist circuit connected to a second end of the bit line pair. This segmentation allows each circuit to independently contribute to pre-charging, improving both speed and uniformity by charging from multiple locations simultaneously.
Solution Approach 2:
The pre-charge assist circuit acts as an intermediary element that facilitates faster pre-charging by providing an additional pre-charging path. It complements the conventional pre-charge circuit, ensuring that both ends of the bit line pair receive adequate charging current to achieve uniform and rapid voltage levels.
2Productivity
If the word line is raised to write or read data, then data can be communicated to or from the memory cell, but the read operation speed is limited by bit line pre-charging efficiency
Solution Approach 1:
The bit lines are pre-charged to the supply voltage level before the word line is raised to initiate read or write operations. The dual pre-charge circuit configuration ensures this preliminary action occurs rapidly and uniformly, reducing the time penalty associated with pre-charging and thereby improving overall read operation speed and productivity.
Data Source
AI summary
A memory device is provided. The memory device includes a memory cell array having a plurality of memory cells arranged in a matrix of a plurality of rows and a plurality of columns. Each of the plurality of columns include a first plurality of memory cells connected to a first bit line and a second bit line. A pre-charge circuit is connected to the memory cell array. The pre-charge circuit pre-charges each of the first bit line and the second bit line from a first end. A pre-charge assist circuit is connected to the memory cell array. The pre-charge assist circuit pre-charges each of the first bit line and the second bit line from a second end, the second end being opposite the first end.