SRAM Global Bit Line Pre-Charge Control for Low Power
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Solution Overview
Problem
Conventional SRAM memory systems experience significant power dissipation during write cycles, especially as clock frequencies increase and SRAM sizes grow, due to the swinging of global bit lines and active clocking circuitry during write operations.
Innovation Solution
The global bit line is prevented from swinging during write operations by modifying the evaluation circuitry to only activate clocking circuitry during read operations and maintaining the global bit line at a pre-charge logic value, even when writing a logic value opposite to the pre-charge logic value.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If conventional evaluation circuitry is used with active clocking during write operations, then data can be written to memory cells, but power dissipation increases significantly due to global bit line swinging
Solution Approach 1:
The patent applies dynamics by making the clock signal conditional rather than continuous. The clock signal is enabled only during read operations and disabled during write operations, allowing the system to adapt its behavior based on the operational mode. This dynamic control eliminates unnecessary clocking activity during writes, reducing power dissipation while maintaining write capability through alternative write paths that do not require global bit line swinging.
Solution Approach 2:
The patent implements periodic action by using clock signals that are activated only during specific read operations rather than continuously. The clocking circuitry operates periodically based on read requirements, remaining inactive during write operations and other periods. This periodic activation pattern reduces overall power consumption by eliminating redundant clocking cycles while ensuring read operations receive necessary clocking for proper evaluation.
2Reliability
If clocking circuitry is continuously active to support read operations, then read evaluation can be performed, but power dissipation increases during write cycles
Solution Approach 1:
The patent makes the clocking circuitry dynamic by enabling it only during read operations and disabling it during write operations. This conditional activation ensures that clocking is present when needed for reliable read evaluation while eliminating unnecessary clocking during writes that would otherwise consume power without providing benefit. The system adapts its clocking behavior to match operational requirements.
Solution Approach 2:
The patent extracts the clocking function from the continuous operational cycle and applies it only where needed - specifically during read operations. By separating the clocking requirement from continuous operation and applying it selectively during reads, the patent eliminates redundant clocking during write operations, reducing power dissipation while maintaining read reliability through targeted clocking activation.
3Loss of information
If global bit line swings during write operations to reflect written data, then data integrity is maintained, but power consumption increases
Solution Approach 1:
The patent segments the bit line evaluation function by introducing local bit line evaluation that operates independently for each memory cell during write operations. Instead of requiring the global bit line to swing and reflect written data, each cell's write operation is evaluated locally at the cell level. This segmentation eliminates the need for global bit line swinging during writes, reducing power dissipation while maintaining data integrity through local verification.
Solution Approach 2:
The patent introduces local evaluation circuitry as an intermediary between the write operation and global bit line evaluation. This local evaluator serves as a mediator that verifies write data integrity at the cell level without requiring the global bit line to swing. The intermediary local evaluation mechanism maintains data integrity information while avoiding the power-consuming global bit line transitions during write operations.
Data Source
AI summary
Methods and apparatus provide for controlling an SRAM memory, the SRAM memory including a plurality of memory cells arranged in an array of rows (word lines) and columns (bit lines), including: mirroring logic values of at least one of the bit lines to a global bit line; driving the global bit line to a pre-charge logic value in response to a clock signal that cycles at least one time during successive read and write operations to the memory cell; maintaining the global bit line at the pre-charge logic value during a write operation in which a logic value is written to the bit line that is opposite to the pre-charge logic value.