SRAM Bit Line Pre-charge Circuit Voltage Switching
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Solution Overview
Problem
Existing methods for reducing power consumption in SRAMs by lowering the voltage of bit line power supplies lead to a decrease in sensing speed due to shared pre-charge power supplies, and using high-voltage power for sense amplifiers increases overall power consumption.
Innovation Solution
A semiconductor storage device with a local sense amplifier, bit lines, pre-charge circuits, and a power-supply-voltage switching circuit that switches between low-voltage and high-voltage power supplies for the sense amplifier and driving circuits, allowing for efficient pre-charging and operation optimization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If a low-voltage power supply is used for bit lines to reduce power consumption, then power consumption is reduced, but sensing speed drops because the pre-charge power supply voltage is also reduced
Solution Approach 1:
The patent divides the pre-charge power supply system into two independent parts: a first pre-charge power supply for bit lines operating at low voltage, and a second pre-charge power supply for sense amplifier bit lines operating at high voltage. This segmentation allows each part to be optimized independently for its specific function, enabling low power consumption for bit lines while maintaining high sensing speed through high-voltage pre-charging of sense amplifier bit lines.
2Speed
If a high-voltage power supply is used for the sense amplifier to maintain sensing speed, then sensing speed is maintained, but overall power consumption increases
Solution Approach 1:
The patent applies different voltage qualities to different parts of the system: low voltage is applied to bit lines where power consumption is the primary concern, while high voltage is applied specifically to sense amplifier bit lines where sensing speed is critical. This local differentiation of voltage quality allows the system to optimize for both low power consumption and high sensing speed simultaneously by matching voltage levels to functional requirements.
3Device complexity
If a shared pre-charge power supply is used for both bit lines and sense amplifier, then device complexity is reduced, but performance optimization is limited
Solution Approach 1:
The patent segments the pre-charge power supply into separate circuits for bit lines and sense amplifier bit lines, with each segment having independent voltage control. This segmentation increases device complexity slightly but enables significant performance optimization by allowing independent voltage optimization for each functional block, thereby improving overall system performance.
Data Source
AI summary
In one embodiment, a semiconductor storage device includes a memory cell, a sense amplifier, a bit line, a pre-charge circuit, and a power-supply-voltage switching circuit. The memory cell is configured to store data. The sense amplifier is configured to amplify a signal from the memory cell. The bit line is configured to transmit the signal from the memory cell to the sense amplifier. The pre-charge circuit is configured to pre-charge the bit line. The power-supply-voltage switching circuit is configured to switch a voltage of a power supply and to actuate the sense amplifier after the bit line is pre-charged by the pre-charge circuit, wherein the power-supply-voltage switching circuit is configured to switch the voltage of the power supply to be larger than a voltage during the pre-charge by the pre-charge circuit.