SRAM Cell Bit Line Segmentation for Data Integrity
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Static random access memory (SRAM) with a small static noise margin is prone to data corruption due to write disturb and read disturb, especially when using a method that shares bit lines for writing and reading, leading to potential data corruption in both selected and non-selected cells.
Innovation Solution
The semiconductor storage device employs a configuration with specific transistor connections and bit line management to isolate write and read operations, preventing data corruption by ensuring that write bit lines are cut off from non-selected cells during writing and read bit lines are isolated during writing, and vice versa, even when the static noise margin is small.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a six-transistor SRAM cell is used, then device complexity is reduced, but data reliability deteriorates due to write disturb and read disturb in non-selected cells
Solution Approach 1:
The patent divides the bit line function into separate write bit lines and read bit lines. Write bit lines are used exclusively for write operations while read bit lines are used exclusively for read operations, preventing the interference that occurs when a single bit line is shared for both operations.
Solution Approach 2:
The patent introduces column selection transistors as intermediary elements between the bit lines and the memory cell. These transistors act as gates that control whether write or read bit lines are connected to the memory cell, enabling isolation of write and read operations even when transfer transistors are turned on in non-selected cells.
2Device complexity
If bit lines are shared for writing and reading, then device complexity is reduced, but data reliability deteriorates due to read disturb in selected cells
Solution Approach 1:
The patent segments the bit line functionality by providing separate write bit lines and read bit lines. This segmentation eliminates the read disturb problem that occurs when read operations are performed on shared bit lines, as write bit lines are never activated during read operations.
Solution Approach 2:
The patent activates column selection transistors in advance to establish the correct connection before write or read operations begin. This preliminary action ensures that only the intended cell is connected to the appropriate bit lines, preventing unintended interference.
3Ease of operation
If transfer transistors are turned on during write and read operations, then ease of operation is improved, but data reliability deteriorates due to noise coupling in non-selected cells
Solution Approach 1:
The column selection transistors serve as intermediary control elements that manage the interaction between transfer transistors and bit lines. Even when transfer transistors are turned on in non-selected cells, the column selection transistors remain off for those cells, blocking noise coupling and preventing data corruption.
Solution Approach 2:
The patent applies local control through column selection transistors that are independently controlled for each memory cell column. This allows transfer transistors to be turned on globally for operational simplicity while maintaining local isolation where needed to prevent noise coupling.
Data Source
AI summary
A memory cell of a static random access memory (SRAM) includes a pair of drive transistors, a pair of load transistors, a pair of write-only transfer transistors, a pair of read-only transfer transistors, a pair of read-only drive transistors, and a pair of column selection transistors. The memory cell also includes a word line, a pair of write bit lines, a pair of read bit lines, and a column selection line.