SRAM Bit-Line Capacitor Structure for Compact Write Assist
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Solution Overview
Problem
The minimum operating voltage (Vmin) of static random access memory (SRAM) is limited by the writability of SRAM bit-cells, necessitating write-assist circuits to enhance writability and increase yield, with existing approaches requiring additional capacitance that occupy significant area.
Innovation Solution
Incorporating conductive lines with lengths greater than twice the length of bit lines to form a capacitor structure, reducing the required area of the control circuit by utilizing these lines as capacitors to adjust voltage levels for write operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If additional capacitance is added to enhance writability of SRAM bit-cells, then the minimum operating voltage (Vmin) is improved, but the control circuit area increases significantly
Solution Approach 1:
The bit lines are designed to serve dual purposes: as signal transmission lines for memory operations and as capacitance storage elements for write-assist operations. By utilizing the inherent capacitance of the bit lines themselves, the patent eliminates the need for separate dedicated capacitance structures, thereby achieving multi-functionality without increasing overall circuit area.
Solution Approach 2:
The bit lines provide their own capacitance service by utilizing their inherent electrical properties. The capacitance naturally present in the bit line structure is leveraged to perform write-assist functions, eliminating the need for external or additional capacitance components. This self-service approach allows the bit lines to contribute to both signal transmission and voltage storage functions.
2Productivity
If write-assist circuits are implemented to improve Vmin, then the yield of SRAM is increased, but the device complexity increases
Solution Approach 1:
The bit lines are designed to serve dual purposes: as signal transmission lines for memory operations and as capacitance storage elements for write-assist operations. By utilizing the inherent capacitance of the bit lines themselves, the patent eliminates the need for separate dedicated capacitance structures, thereby achieving multi-functionality without increasing overall circuit area.
Solution Approach 2:
The bit lines provide their own capacitance service by utilizing their inherent electrical properties. The capacitance naturally present in the bit line structure is leveraged to perform write-assist functions, eliminating the need for external or additional capacitance components. This self-service approach allows the bit lines to contribute to both signal transmission and voltage storage functions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution reduces the area needed for the control circuit while effectively enhancing the writability of SRAM bit-cells, thus improving yield without increasing circuit size.
Implementation Method 1
Incorporating conductive lines with lengths greater than twice the length of bit lines to form a capacitor structure
Data Source
AI summary
A semiconductor device includes a first memory array, a first bit line, a second memory array, a second bit line, a first conductive line and a first control circuit. The first bit line crosses over and is coupled to the first memory array, and extends along a first direction. The second bit line crosses over the second memory array, and is coupled to the first bit line. The first conductive line crosses over the second memory array and a part of the first memory array, and is configured to operate as a part of a first capacitor. The first control circuit is configured to couple the first conductive line to the second bit line when the first memory array is written.