SRAM Bit Cell Backside Power Mesh for Lower Metal Resistance
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Solution Overview
Problem
The existing integrated circuit manufacturing processes face challenges in optimizing the layout and connectivity of semiconductor devices, particularly in the back-end-of-line (BEOL) phase, which affects the speed and efficiency of signal transmission due to high metal resistance and power IR drop.
Innovation Solution
The proposed solution involves flipping the memory device upside down after the front-side process, thinning the substrate, and forming backside metal structures to reduce metal resistance and power IR drop by placing supply voltage metal lines on the backside, thereby creating a robust power mesh and improving signal transmission speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If metal layers are formed on the front side only, then the manufacturing process is simpler, but the metal resistance and power IR drop increase
Solution Approach 1:
The patent applies dimensionality change by transitioning from a single-sided (front side only) metal layer configuration to a dual-sided (front side and back side) configuration. Specifically, the back side of the semiconductor device is flipped and additional metal layers are formed on this second surface, creating a three-dimensional interconnect structure that reduces resistance and IR drop while maintaining manufacturing feasibility through sequential processing steps
2Reliability
If metal line width is increased to reduce resistance, then the electrical performance improves, but the layout area increases
Solution Approach 1:
The patent resolves this contradiction by utilizing the back side of the device as an additional dimensional space for routing metal interconnects. This allows the creation of wider metal lines and power rails on the second surface without increasing the device's footprint area, effectively reducing resistance and improving electrical performance while maintaining compact layout
3Reliability
If the substrate is thinned and backside structures are formed, then the metal resistance and IR drop are reduced, but the manufacturing complexity increases
Solution Approach 1:
The patent applies preliminary action by performing substrate thinning and backside surface preparation steps before forming the metal layers on the second surface. This sequencing of operations - flipping the device, thinning the substrate, and then proceeding with metal deposition - allows the complex backside processing to be completed in advance, facilitating subsequent metal layer formation and reducing overall manufacturing complexity
Data Source
AI summary
A semiconductor device is provided. The semiconductor device comprises a bit cell comprising first and second inverters and a first transistor. The first inverter comprising a second transistor and a third transistor that share a first gate structure extending along a first direction. The second transistor is coupled to a first metal line in a backside of the semiconductor device to receive a first supply voltage. The second inverter is cross-coupled with the first inverter and comprises a fourth transistor and a fifth transistor that share a second gate structure extending along the first direction. The first transistor and second transistors share a first active area extending along a second direction. The first transistor receives first data from a first bit line in a front side of the semiconductor device.