SRAM Bit Cell Layout With Backside Power Rails
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Solution Overview
Problem
Existing semiconductor devices and fabrication methods face challenges in efficiently scaling down while maintaining complexity and functionality, particularly in the integration of SRAM bit cells, due to limitations in interconnect layouts and power rail configurations.
Innovation Solution
The SRAM bit cell design incorporates a back side power rail configuration with bit-line and word-line conductors on the front side, utilizing a unique interconnect layout that includes both front and back side interconnect structures, allowing for a cell height equal to four times the gate pitch, and employing GAA transistors for enhanced performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If conventional interconnect layouts are used, then manufacturing process is simpler, but cell size and functional density are limited
Solution Approach 1:
The patent introduces a back-side interconnect structure that utilizes the third dimension (vertical stacking) by placing power rails and ground rails on the back side of the semiconductor substrate while keeping bit lines and word lines on the front side. This dimensional separation allows for reduced cell footprint without increasing lateral interconnect complexity, as power distribution is handled independently on the back side.
Solution Approach 2:
The interconnect structure is segmented into front-side components (bit lines, word lines, contact holes) and back-side components (power rails, ground rails). This segmentation allows each side to be optimized independently - the front side for signal routing and the back side for power distribution - thereby reducing overall cell size without compromising manufacturing simplicity.
2Productivity
If functional density is increased, then production efficiency improves, but manufacturing precision requirements increase
Solution Approach 1:
By moving power rails to the back side, the patent enables higher functional density on the front side without proportionally increasing manufacturing precision requirements. The vertical separation means that tighter lateral spacing on the front side does not directly translate to tighter spacing requirements for power distribution, as that is handled on the back side where larger feature sizes can be maintained.
3Area of stationary object
If cell height is reduced to four times gate pitch, then area efficiency improves, but interconnect integration complexity increases
Solution Approach 1:
The back-side power rail configuration enables the cell height to be reduced to four times the gate pitch by utilizing vertical space more efficiently. Power connections are made through contact holes that penetrate through the substrate thickness, allowing compact lateral dimensions while maintaining adequate power distribution through the third dimension.
Data Source
AI summary
An integrated circuit chip includes: an array of memory bit cells arranged in columns and rows. Each memory bit cell includes: first and second fin structures extending along a first direction; first, second, third and fourth gate structures parallelly arranged along a second direction substantially perpendicular to the first direction; a bit line conductor extending along the first direction; a bit line bar conductor extending along the first direction; a first word line extending along the second direction; and a second word line extending along the second direction. The first word line is electrically connected to the memory bit cell, and the second word line is connected to an adjacent memory bit cell of the array of memory bit cells in a same row. A supply voltage line extends along the first direction and underlies the first fin structure.