SRAM Bit Cell Layout With Lower Wordline-Bitline Coupling
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Solution Overview
Problem
SRAM cells require more silicon area than DRAM due to their six-transistor structure, and there is a need to reduce power consumption and increase data storage density in portable electronics and high-speed computation systems, while maintaining fast access times.
Innovation Solution
A mixed transistor type SRAM bit cell with reduced coupling capacitance is achieved by vertically stacking the wordline and bitline further apart, using additional metallization levels and jumper structures that do not overlap with the bitlines, thereby minimizing coupling capacitance and optimizing the balance between capacitance and resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If wordline and bitline are placed closer together to reduce area, then area is reduced, but coupling capacitance increases causing higher power consumption and slower access times
Solution Approach 1:
The patent resolves the area-capacitance contradiction by transitioning from a planar layout to a three-dimensional stacked metallization structure. Wordline and bitline are separated into different vertical metallization levels, allowing them to be physically closer in the lateral plane (reducing area) while maintaining adequate vertical separation (reducing coupling capacitance). This dimensional transition enables simultaneous optimization of both area and power consumption.
2Area of moving object
If wordline and bitline are vertically stacked closer to reduce area, then area is reduced, but coupling capacitance increases causing slower access times
Solution Approach 1:
The patent applies dimensional separation by placing wordline and bitline in different vertical metallization levels. This allows lateral proximity for area reduction while maintaining vertical spacing for signal speed, as the coupling capacitance between non-overlapping metallization levels is minimized despite reduced lateral dimensions.
3Use of energy by moving object
If additional metallization levels are added to separate wordline and bitline, then coupling capacitance is reduced, but device complexity increases
Solution Approach 1:
The additional metallization levels serve multiple functions simultaneously: they provide physical separation between wordline and bitline to reduce coupling capacitance, enable vertical stacking for area reduction, and maintain signal integrity through controlled impedance routing. This multi-functionality justifies the increased structural complexity by delivering multiple performance benefits from a single architectural approach.
Data Source
AI summary
The current disclosure is directed to a SRAM bit cell having a reduced coupling capacitance. In a vertical direction, a wordline “WL” and a bitline “BL” of the SRAM cell are stacked further away from one another to reduce the coupling capacitance between the WL and the BL. In an embodiment, the WL is vertically spaced apart from the BL with one or more metallization level that none of the WL or the BL is formed from. Connection island structures or jumper structures are provided to connect the upper one of the WL or the BL to the transistors of the SRAM cell.