SRAM Bit Cell Layout With Split Power Rails for Compact Interconnects
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Solution Overview
Problem
The development of vertically stacked semiconductor devices for SRAM bit cells faces challenges in forming efficient electrical interconnection structures, particularly with reduced cell area, as existing designs require vertical interconnects that can be difficult to precision-engineer and may lead to electrical resistance imbalances between different vertical levels.
Innovation Solution
The bit cell design arranges one power supply above and one below the cell, reducing the need for extensive vertical interconnects and allowing for more precise connection of transistors, while using dielectric walls to separate gate electrodes, enabling tighter spacing between channel tracks and reducing the complexity of lithographic patterning.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If vertically stacked transistor design is used to reduce cell area, then area efficiency is improved, but formation of electrical interconnection structures becomes more difficult
Solution Approach 1:
The patent transitions from planar interconnection to three-dimensional stacked architecture, arranging transistor channels at different vertical levels (first level and second level) to achieve area reduction while managing interconnections through vertical vias between levels
Solution Approach 2:
The bit cell is segmented into multiple vertical levels with distinct functional regions: lower transistors at first level, upper transistors at second level, with separate power supply tracks (first power supply track below lower transistor, second power supply track above upper transistor) to simplify interconnection formation
2Area of stationary object
If cell area is reduced through scaling, then area efficiency is improved, but available space for interconnecting structures is reduced
Solution Approach 1:
Interconnecting structures are arranged in three dimensions with power supply tracks positioned above and below transistor levels, utilizing vertical space rather than horizontal plane to maintain connection space as cell area shrinks
Solution Approach 2:
The patent nests interconnection structures within the vertical profile of the bit cell, with first power supply extending below lower transistor and second power supply extending above upper transistor, effectively nesting power delivery paths within the stacked transistor architecture
3Area of stationary object
If vertical interconnects are used to connect transistors to power supply, then area efficiency is improved, but precision engineering difficulty increases
Solution Approach 1:
Power supply tracks are positioned and formed in advance at optimal locations (first power supply track below lower transistor, second power supply track above upper transistor) to simplify subsequent via formation and reduce precision requirements for vertical interconnect alignment
Solution Approach 2:
Horizontal power supply tracks serve as intermediary structures between the substrate and upper transistor levels, providing stable reference planes that simplify the formation of vertical vias and reduce manufacturing precision challenges
4Device complexity
If power supplies are arranged on one side of bit cell, then layout simplicity is improved, but vertical interconnect length increases
Solution Approach 1:
The patent employs asymmetric power supply arrangement with first power supply positioned below lower transistor and second power supply positioned above upper transistor, creating balanced via lengths from each transistor level to its nearest power supply rather than uniform long vias to a single-sided power rail
Solution Approach 2:
Power supplies are distributed across multiple vertical levels rather than confined to a single horizontal plane, with first power supply at lower level and second power supply at upper level, reducing vertical interconnect length by matching power delivery proximity to transistor operating levels
Data Source
Figure 1a~1b
Figure 2a
Figure 2b
AI summary
A bit cell (10) for a Static Random-Access Memory, SRAM, is provided, comprising first and second sets of transistors. Each set comprises a pass-gate transistor (PG1, PG2) and a stacked complementary transistor pair of an upper transistor (11, 21) and a lower transistor (12, 22). A source/drain terminal of a lower transistor of each set of transistors is connected to a respective first power supply (31) extending in a first power supply track arranged below the lower transistor, whereas a source/drain terminal of an upper transistor of each set of transistors is connected to a respective second power supply (32) extending in a second power supply track arranged above the upper transistor.