SRAM Write Assist Circuit Using Bit Cell Voltage Division
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Solution Overview
Problem
Existing SRAM memory devices face challenges in achieving faster write speeds while maintaining signal integrity, as traditional LCV write assist circuits increase the silicon footprint of integrated circuits.
Innovation Solution
The implementation of an LCV write assist circuit using SRAM bit cell transistors, which operates as a voltage divider to reduce the SRAM core voltage during write operations, allowing for faster write speeds without compromising signal integrity and reducing the overall silicon footprint by sharing the same semiconductor layout as SRAM bit cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If traditional LCV write assist circuits are implemented, then write speed is improved, but silicon footprint increases
Solution Approach 1:
The patent merges the LCV write assist circuit with the SRAM bit cell structure by sharing the same semiconductor layout. The write assist transistors are integrated within the same array structure as the storage bit cells, allowing the write assist functionality to be combined with the storage structure, thereby reducing the overall silicon footprint while maintaining fast write capability
Solution Approach 2:
The patent creates multi-functional transistors that serve dual purposes: SRAM bit cell transistors function as both storage elements and LCV write assist transistors. This universal design allows the same hardware structure to perform multiple functions (storage and write assistance), eliminating the need for separate dedicated write assist circuits and reducing area
2Area of stationary object
If SRAM transistors are made smaller to increase integration density, then area is reduced, but signal integrity deteriorates
Solution Approach 1:
The patent applies local quality by providing different voltage conditions to different parts of the circuit during write operations. The LCV (lower core voltage) is applied specifically to the write assist transistors during write operations, while the rest of the SRAM array operates at normal voltage. This localized voltage adjustment enables smaller transistor dimensions while maintaining signal integrity through enhanced write capability in the specific region where it is needed
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables faster write speeds in SRAM memory devices while maintaining signal integrity and reducing the silicon footprint, making it area-efficient and suitable for high-performance applications.
Implementation Method 1
operates as a voltage divider to reduce the SRAM core voltage during write operations
Data Source
AI summary
A semiconductor memory device includes an array of memory cells arranged in a plurality of rows and columns, with each memory cell including a plurality of bit cell transistors. The semiconductor memory device further includes a plurality of write assist circuits, including one or more write assist circuits within each column of the array of memory cells, each write assist circuit configured to provide a core voltage to memory cells within the same column and to reduce the core voltage during a write operation. The array of memory cells and the plurality of write assist circuits have a common semiconductor layout.