SRAM Global Bitline Biasing for Leakage-Stable Readout
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Solution Overview
Problem
The global bitline in multi-banked memory systems experiences leakage issues due to process, voltage, and temperature variations, leading to erroneous readings during memory access operations, particularly during read evaluation 0 operations, where the bitline may discharge prematurely, causing incorrect detection of stored bit values.
Innovation Solution
The implementation of a dynamic source bias circuitry on output transistors, which applies a global read evaluation signal or stored bit values as a source bias, replaces the conventional keeper circuit, thereby reducing leakage and sustaining a high binary voltage level on the global bitline, ensuring accurate bit value sensing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional keeper circuit is used on the global bitline, then the bitline state is retained when not actively driven, but leakage current causes the bitline to transition to low erroneously under PVT variations
Solution Approach 1:
The patent changes the operational parameters of the output transistor by applying a dynamic source bias voltage to the keeper transistor. This bias voltage is adjusted based on process, voltage, and temperature conditions to optimize the keeper transistor's ability to counteract leakage current while maintaining stability across PVT variations
Solution Approach 2:
The keeper circuit transitions from a static design to a dynamic one where the source bias voltage is continuously adjusted based on operating conditions. The dynamic biasing mechanism allows the keeper transistor to adapt its strength to counteract varying leakage currents under different PVT conditions, improving reliability without increasing static power consumption
2Reliability
If a keeper device pulls the global bitline high, then the bitline state is maintained, but contention occurs with the bitline pull-down device during read operations
Solution Approach 1:
The patent applies preliminary action by pre-biasing the keeper transistor's source terminal before the read operation begins. This dynamic source bias is established in advance and adjusted based on the operational mode, allowing the keeper transistor to be selectively strengthened or weakened to prevent contention with pull-down devices during read operations while maintaining state stability during retain operations
3Adaptability or versatility
If the keeper device works across wide PVT variations, then state retention is maintained, but timing constraints and design complexity increase
Solution Approach 1:
The patent implements self-service through a dynamic biasing mechanism that automatically adjusts the keeper transistor's source bias voltage based on operating conditions. The bias circuit responds to PVT variations and operational mode changes without requiring complex external control logic, allowing the keeper circuit to adapt to wide PVT variations while maintaining relatively simple design
Data Source
AI summary
A static random access memory (SRAM) or other bit-storing cell arrangement includes memory cells and a hierarchical bitline structure including local bitlines for subsets of the memory banks and a global bitline spanning the subsets. A keeper circuit for the global bitline is replaced by bias circuitry on output transistors of the memory cells.