SRAM Bit-Line Arithmetic for Precise Charge Sharing
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Solution Overview
Problem
Current arithmetic devices using SRAM struggle with improving arithmetic precision and reducing read disturb during operations, particularly in multi-bit operations where charge sharing and bit shifting are complex.
Innovation Solution
The device employs a multi-tiered bit line structure with local and global bit lines connected via switching circuits, allowing for charge sharing and precise voltage transitions, and incorporates a controller to manage bit shifting based on weights assigned to SRAM cells for improved precision and reduced read disturb.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If multi-bit operations are performed in SRAM-based arithmetic devices, then arithmetic precision can be improved, but charge sharing and bit shifting become complex
Solution Approach 1:
The bit lines are divided into multiple segments (first bit line, second bit line, third bit line) with different functions. The first and second bit lines are used for reading data from different SRAM cells, while the third bit line serves as a shared accumulation line. This segmentation allows multi-bit operations to be performed systematically, improving arithmetic precision while managing operational complexity through structured organization.
Solution Approach 2:
The patent introduces a time dimension to the bit line structure by dynamically switching between coupled and decoupled states. The switching circuit transitions the bit lines between different connection configurations during different phases of the operation cycle, enabling complex multi-bit arithmetic operations to be decomposed into manageable sequential steps, thereby improving precision without overwhelming complexity.
2Measurement precision
If voltage transitions are made precise in SRAM operations, then arithmetic precision is improved, but read disturb increases
Solution Approach 1:
The switching circuit acts as an intermediary between the bit lines and the SRAM cells. It controls the coupling and decoupling of bit lines, enabling precise voltage transitions only when needed for reading valid data. This intermediary function allows the system to achieve precise voltage control for arithmetic operations while minimizing unnecessary voltage transitions that would cause read disturb, thus resolving the contradiction between precision and harmful effects.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances arithmetic precision by stabilizing voltage transitions and reducing read disturb through controlled charge sharing and bit shifting, leading to more accurate signal accumulation and processing.
Implementation Method 1
a first transistor electrically coupled between the first memory cell and the first bit line; a controller configured to set a conduction state between the first memory cell and the first bit line by the first transistor
Implementation Method 2
a first switching circuit electrically coupled between the first bit line and the third bit line, the first switching circuit being configured to switch between the first bit line and the third bit line to either a coupled state or a decoupled state
Data Source
AI summary
An arithmetic device includes a first memory cell, a first bit line, a first transistor, a second memory cell, a second bit line, a second transistor, a third bit line, a first switching circuit, a second switching circuit and a controller. The controller sets a conduction state between the first memory cell and the first bit line by the first transistor, and sets a conduction state between the second memory cell and the second bit line by the second transistor. The controller sets the first switching circuit and the second switching circuit in a coupled state and sets the conduction state between the first bit line and the third bit line and between the second bit line and the third bit line to transition voltages of the first, second and third bit lines to a first voltage.