SRAM Bit Line Charge Sharing for RSNM and Bit Flip Control
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Solution Overview
Problem
Inconsistent fabrication of memory cells due to silicon process variation, operation voltage, and temperature corners leads to read static noise margin (RSNM) violations, causing unintentional bit flips in SRAM cells, which existing methods to address this issue, such as changing metal schemes or reducing word line driver size, result in signal integrity or performance degradation.
Innovation Solution
Implementing a programmable charge sharing (CS) capacitor to connect bit lines and bit line bars to programmable bit lines and bars, reducing voltage on these lines through charge sharing, thereby minimizing current influx and preventing unintentional bit flips.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If existing methods such as changing metal schemes or reducing word line driver size are used to address RSNM violations, then bit flip prevention is improved, but signal integrity or performance degrades
Solution Approach 1:
The patent introduces a charge sharing capacitor as an intermediary component between the bit line and ground. This capacitor shares excess charge from the bit line during read operations, preventing voltage bounce that causes bit flips, without requiring changes to the word line driver or metal scheme. The intermediary capacitor resolves the contradiction by providing RSNM improvement while maintaining signal integrity of the original driver circuitry.
2Reliability
If existing methods such as changing metal schemes or reducing word line driver size are used to address RSNM violations, then bit flip prevention is improved, but device performance degrades
Solution Approach 1:
The charge sharing capacitor acts as a mediator that improves reliability without impacting the performance of the word line driver. By placing the capacitor at the bit line node rather than modifying the driver, the patent achieves RSNM improvement while maintaining the original performance characteristics of the memory read operation.
3Reliability
If charge sharing capacitor is used to reduce voltage bounce, then RSNM is improved, but device area increases
Solution Approach 1:
The patent optimizes the charge sharing capacitor's parameters (capacitance value, connection timing) to achieve adequate RSNM improvement with minimal area overhead. By carefully selecting the capacitor size and control signal timing, the design balances reliability improvement against area consumption, ensuring the capacitor is large enough to prevent bit flips but small enough to minimize area impact.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The programmable charge sharing capacitor reduces voltage bounce at the drain of pull-down resistors, increasing the read static noise margin (RSNM) and minimizing the probability of bit flips, without degrading performance or area.
Implementation Method 1
a charge sharing circuit connected to the bit line and the first programmable bit line. The charge sharing circuit is configured to transfer a charge from the bit line to the first programmable bit line
Implementation Method 2
a discharge circuit connected to the first programmable bit line, the discharge circuit configured to discharge a stored charge in the first programmable bit line
Data Source
AI summary
A memory device and a method of operating the memory device are disclosed. In one aspect, the memory device includes a bit line connected to a plurality of memory cells of a memory array, the bit line having a first length. The memory device includes a first programmable bit line having a second length determined based on a size of the memory array, and a charge sharing circuit connected to the bit line and the first programmable bit line. The charge sharing circuit is configured to transfer a charge from the bit line to the first programmable bit line. The memory device includes a discharge circuit connected to the first programmable bit line, the discharge circuit configured to discharge a stored charge in the first programmable bit line.