SRAM Bit Line Read Circuit for In-Memory Compute Accuracy
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Solution Overview
Problem
Variation in read current during simultaneous access of multiple rows in an SRAM array for in-memory compute operations adversely affects measurement accuracy.
Innovation Solution
Implement a read circuit with dual voltage sensing circuits and a processing circuit that averages the sensed signals to reduce sensitivity to current variations, and a testing circuit to identify the less variable bit line for use in read operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple rows are simultaneously accessed for in-memory compute operations, then productivity is improved, but measurement precision deteriorates due to read current variation
Solution Approach 1:
The patent implements a feedback mechanism where the actual read current is measured during the compute operation, and this measurement is used to dynamically adjust the reference current or compensation values. This closed-loop approach compensates for current variations caused by simultaneous row access, thereby maintaining measurement precision while enabling high-productivity parallel operations.
Solution Approach 2:
The patent changes the parameter of reference current or threshold voltage dynamically based on the number of simultaneously accessed rows. By adjusting these parameters in response to the operational conditions, the system compensates for current variation effects, allowing multiple rows to be accessed simultaneously without sacrificing read accuracy.
2Measurement precision
If read circuit complexity is increased to account for current variation, then measurement precision is improved, but device complexity worsens
Solution Approach 1:
The patent divides the read circuit into multiple independent sensing units, each capable of measuring current on individual bit lines. By segmenting the sensing function, the system can process multiple rows in parallel while maintaining accuracy for each, avoiding the need for a single complex centralized sensing circuit.
Solution Approach 2:
The patent introduces intermediary compensation circuits or reference current sources that mediate between the variable read current and the decision logic. These intermediaries absorb the variation effects, allowing the core read circuit to remain relatively simple while still achieving high measurement precision through the intermediary's current equalization or differential sensing function.
Data Source
AI summary
An in-memory computation circuit includes a memory array with SRAM cells connected in rows by word lines and in columns by bit lines. A row controller circuit simultaneously actuates word lines in parallel for an in-memory compute operation. A column processing circuit includes a read circuit that operates to reduce sensitivity to variation in bit line read current. Additionally, a testing circuit senses analog signals on the complementary bit lines to identify one of the complementary bit lines as having a less variable read current. That identified one of the complementary bit lines is coupled to the read circuit for the in-memory compute operation.