SRAM Bit Line Layout Using Frontside and Backside Routing
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Solution Overview
Problem
Existing memory circuits face challenges in reducing parasitic resistive and capacitive bit line loading, which affects speed and power performance during read and write operations.
Innovation Solution
The implementation of a memory macro with separate frontside and backside bit line connections for static random-access memory (SRAM) cells using complementary field effect transistor (CFET) devices, where stacked pass gates connect adjacent cells to either a frontside or backside bit line, maintaining memory cell density and improving performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If separate frontside and backside bit line connections are implemented, then parasitic resistive and capacitive loading is reduced and speed performance is improved, but device complexity increases
Solution Approach 1:
The bit line connections are segmented into separate frontside and backside paths. The frontside bit line connects to first subsets of memory cells while the backside bit line connects to second subsets, dividing the original single bit line into multiple independent segments that can operate simultaneously, thereby reducing parasitic loading and improving speed.
Solution Approach 2:
The connection structure transitions from a two-dimensional planar layout to a three-dimensional configuration by utilizing both the frontside and backside of the semiconductor substrate. This vertical stacking of bit line connections in the third dimension allows parallel data paths without increasing lateral footprint.
2Quantity of substance
If stacked pass gates are used to connect adjacent cells to frontside or backside bit lines, then memory cell density is maintained, but manufacturing complexity increases
Solution Approach 1:
Multiple pass gates are stacked vertically and merged into a single compact structure. The first and second pass gates are positioned one above the other, sharing common electrical connections and physical space, which maintains high memory cell density while enabling selective connection to frontside or backside bit lines.
Solution Approach 2:
The pass gates are nested in a stacked configuration where one pass gate is positioned within the vertical space of another. This nesting arrangement allows multiple switching elements to occupy a minimal footprint area, preserving memory cell density while providing the functionality needed for dual-sided bit line connections.
Data Source
AI summary
A memory macro includes an input/output (I/O) circuit positioned in a semiconductor wafer, a column of memory cells including first and second subsets of contiguous memory cells extending away from the I/O circuit in the semiconductor wafer, wherein the first subset is positioned between the I/O circuit and the second subset, a first bit line coupled to the I/O circuit and extending on one of a frontside or a backside of the semiconductor wafer along the first subset and terminating at the second subset, and a second bit line coupled to the I/O circuit and extending on the other of the frontside or the backside along the first and second subsets. Each memory cell of the first subset is electrically connected to the first bit line, and each memory cell of the second subset is electrically connected to the second bit line.