SRAM Bitline Floating Precharge Circuit for Idle Power Reduction
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Solution Overview
Problem
Conventional SRAM cell designs in programmable logic devices waste power due to bitlines being precharged when not in use, leading to leakage between SRAM cells and bitline precharge circuitry.
Innovation Solution
Implementing a precharge circuit that precharges bitlines immediately before read and write operations and floats them at other times to reduce power consumption during power-saving modes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If bitlines are precharged to a high voltage state when not in use, then the bitlines are ready for immediate read or write operations, but power is wasted due to leakage between SRAM cells and bitline precharge circuitry
Solution Approach 1:
The patent applies the dynamics principle by making the bitline precharge circuit dynamic rather than static. The precharge circuit is enabled only during active read/write operations and disabled during idle periods, allowing the system to adapt its power consumption state based on operational requirements. This resolves the contradiction by eliminating continuous precharge during idle states (reducing power loss) while maintaining precharge capability when operations are needed (preserving speed readiness).
Solution Approach 2:
The patent changes the voltage parameter of the bitlines dynamically. During idle periods, bitlines are floated or discharged to low voltage to minimize leakage power consumption. During active operations, bitlines are precharged to high voltage state to enable proper read/write operations. This parameter change approach resolves the contradiction by adjusting the voltage state based on operational needs, reducing power loss during idle while maintaining operational readiness.
2Reliability
If bitlines are precharged continuously, then power is always available for immediate operations, but leakage current increases between SRAM cells and bitline precharge circuitry
Solution Approach 1:
The patent implements periodic action by enabling the precharge circuit only during specific operational periods (read/write operations) rather than continuously. The precharge function is activated periodically when needed and deactivated during idle periods, reducing leakage current while maintaining operational reliability when operations occur. This periodic activation resolves the contradiction between continuous availability and power consumption.
Solution Approach 2:
The patent makes the precharge circuit dynamic by controlling its enable/disable state based on operational requirements. The circuit transitions between active and inactive states, ensuring bitlines are precharged only when operations are initiated. This dynamic control maintains reliability during operations while minimizing leakage power consumption during idle periods, resolving the stated contradiction.
Data Source
AI summary
Techniques are provided which may be used to reduce power consumed by memory circuits. In one example, a memory circuit includes a static random access memory (SRAM) cell. A pair of bitlines are connected to the SRAM cell. A precharge circuit is connected to the bitlines. The precharge circuit is adapted to precharge the bitlines immediately prior to read and write operations performed on the SRAM cell and float relative to the bitlines at other times.