SRAM Read Bit Line Precharge for Lower Memory Power
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Solution Overview
Problem
The high power consumption of static random access memory (SRAM) units during frequent read/write operations, particularly in scenarios like neural networks, limits processing speed and efficiency.
Innovation Solution
An SRAM unit design that adjusts its working structure based on the data distribution in the storage array, precharging or pre-discharging the read bit line accordingly to minimize energy consumption during read operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If conventional 6T-SRAM unit is used with frequent read/write operations, then data storage and retrieval function is maintained, but power consumption increases significantly due to bit line charging and discharging
Solution Approach 1:
The patent applies dynamics by making the bit line precharge state adjustable based on the stored data value. The circuit dynamically selects between precharging the bit line to high level (for storing '0') or keeping it at low level (for storing '1'), allowing the system to adapt its operating state to minimize energy consumption while maintaining read/write functionality
Solution Approach 2:
The patent changes the parameter of bit line initial voltage level based on the data to be stored. By controlling the precharge transistor to set the bit line to different initial states (high or low) depending on the stored bit value, the system optimizes the energy required for subsequent read operations, reducing unnecessary charging cycles
2Use of energy by moving object
If bit line is precharged to high level for every read operation, then read operation can be performed, but energy is consumed even when reading '1' which should maintain high level
Solution Approach 1:
The patent applies preliminary action by precharging the bit line to a specific level based on the stored data before the read operation occurs. If '0' is stored, the bit line is precharged to high level; if '1' is stored, it remains at low level. This preliminary setup eliminates unnecessary charging during read operations, saving energy while maintaining operational simplicity through automated control
Data Source
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AI summary
A static random access memory SRAM unit and a related apparatus are provided, to reduce power consumption of an SRAM when the SRAM memory is accessed. The SRAM unit is located in an SRAM memory, and the SRAM memory includes an SRAM storage array including a plurality of SRAM units. The SRAM unit includes: a storage circuit, connected to each of a write circuit and a read circuit, and configured to store data; the write circuit, configured to write data into the storage circuit; and the read circuit, configured to: after a read enabling signal is valid, enable data on a read bit line connected to the SRAM unit to be the data stored in the storage circuit, where when a first quantity of SRAM units that store the first data and that are in a column of the SRAM unit is greater than a second quantity of SRAM units that store the second data and that are in the column, the read bit line is precharged to a high level; and when the first quantity is less than the second quantity, the read bit line is pre-discharged to a low level.