Ultra Low-Voltage SRAM Bitline Pre-Charge for Stable Reads
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional SRAM circuits face issues with stable operation when there is a significant difference between the memory array supply voltage (VDDMA) and the peripheral supply voltage (VDDMP), leading to unintended state changes in bitcells due to the pass gate transistor turning on during read operations.
Innovation Solution
The implementation of pre-charge circuits and pre-charge assist circuits that pre-charge bitlines to a voltage higher than the peripheral supply voltage (VDDMP) using transistors and capacitors, ensuring bitlines remain at a sufficient voltage to prevent unintended state changes during read operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If VDDMP is reduced to minimize power consumption, then power savings are achieved, but bitcell stability deteriorates due to unintended state changes during read operations
Solution Approach 1:
The pre-charge circuit performs preliminary action by charging the bitline to a high voltage level before the read operation begins. This preliminary charging ensures that when the pass gate transistor activates during reading, the bitline already maintains sufficient voltage to prevent unintended bitcell state changes, thereby enabling low VDDMP operation without compromising reliability
Solution Approach 2:
The pre-charge circuit acts as an intermediary mechanism between the low VDDMP supply and the bitline charging requirement. It uses additional voltage from VDDMA through controlled transistor switching to create an intermediate high-voltage state on the bitline, mediating between the conflicting requirements of low power consumption and stable reading
2Loss of energy
If VDDMA is significantly higher than VDDMP, then power consumption is reduced, but read operation stability worsens due to pass gate transistor leakage
Solution Approach 1:
The pre-charge circuit performs preliminary charging of the bitline to a high voltage level before the read operation. This ensures that during the read operation, even though VDDMA >> VDDMP causes pass gate transistor leakage, the bitline maintains sufficient voltage to prevent unintended state changes in the bitcell
Solution Approach 2:
The invention changes the voltage parameter of the bitline dynamically. Instead of using a fixed voltage level, the bitline is charged to a high voltage level during pre-charge phase, then maintained at this elevated level during the read operation through controlled transistor switching, allowing the system to tolerate the voltage differential between VDDMA and VDDMP
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables stable SRAM operation with a large voltage differential between VDDMA and VDDMP, providing performance gains of over 60% and 100% dynamic power savings by maintaining bitline voltages above VDDMP, thus preventing bitcell state changes.
Implementation Method 1
The implementation of pre-charge circuits and pre-charge assist circuits that pre-charge bitlines to a voltage higher than the peripheral supply voltage (VDDMP) using transistors and capacitors
Data Source
AI summary
Disclosed herein a static random-access memory (SRAM) circuits designed to operate reliably in scenarios where the memory array supply voltage (VDDMA) significantly exceeds the peripheral circuit supply voltage (VDDMP). Various configurations of pre-charge and pre-charge assist circuits are disclosed, each aimed at preventing unintended state changes in bitcells during read operations. These circuits employ techniques such as charge transfer from a higher voltage domain, capacitive coupling, and sense amplifier decoupling to boost bitline voltages above VDDMP during critical read phases. This enables stable SRAM operation with a large voltage differential between VDDMA and VDDMP, facilitating improvements in both performance and power efficiency.