SRAM Bitline Pre-Charge Assist for Low-Voltage Read Stability
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional SRAM circuits face issues with stable operation when there is a significant difference between the memory array supply voltage (VDDMA) and the peripheral supply voltage (VDDMP), leading to unintended state changes in bitcells due to the pass gate transistor PG2 turning on during read operations.
Innovation Solution
The SRAM circuit employs pre-charge assist circuits and capacitive coupling to pre-charge bitlines to a voltage higher than the peripheral supply voltage (VDDMP) using transistors and capacitors, ensuring bitlines remain at a stable voltage during read operations, preventing unintended state changes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If VDDMP is reduced to lower power consumption, then energy efficiency is improved, but bitcell stability deteriorates due to pass gate transistor leakage
Solution Approach 1:
The bitlines are pre-charged to a voltage higher than VDDMP (specifically to VDDMP plus a boost voltage) before the read operation begins. This preliminary action ensures that even when the pass gate transistor leaks current during the read operation, the bitline voltage remains sufficient to maintain bitcell stability throughout the operation.
Solution Approach 2:
The invention applies a boost voltage to counteract the harmful effect of pass gate transistor leakage before it can cause bitcell instability. By pre-charging the bitlines to a voltage level that compensates for the expected leakage current, the system prevents the bitcell state from flipping during the read operation.
2Speed
If VDDMA is significantly higher than VDDMP to improve performance, then read speed is improved, but bitcell stability deteriorates due to unintended state changes
Solution Approach 1:
The invention changes the voltage parameter of the bitlines by applying a boost voltage on top of VDDMP. This parameter change allows the system to maintain bitcell stability even when VDDMA is significantly higher than VDDMP, enabling high-performance operation without sacrificing reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables stable SRAM operation with a large voltage differential between VDDMA and VDDMP, providing performance gains and power efficiency improvements, maintaining read stability without complex voltage shifting circuits.
Implementation Method 1
pre-charge circuit arrangements configured to pre-charge bitlines of the memory array to a voltage higher than the peripheral supply voltage during a read operation
Data Source
Figure 1~3
Figure 4~5
Figure 4A
AI summary
Disclosed herein a static random-access memory (SRAM) circuits designed to operate reliably in scenarios where the memory array supply voltage (VDDMA) significantly exceeds the peripheral circuit supply voltage (VDDMP). Various configurations of pre-charge and pre-charge assist circuits are disclosed, each aimed at preventing unintended state changes in bitcells during read operations. These circuits employ techniques such as charge transfer from a higher voltage domain, capacitive coupling, and sense amplifier decoupling to boost bitline voltages above VDDMP during critical read phases. This enables stable SRAM operation with a large voltage differential between VDDMA and VDDMP, facilitating improvements in both performance and power efficiency.