SRAM Bit-Line Pre-Charging via Charge Sharing for Lower Power
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Solution Overview
Problem
Existing SRAM devices face challenges in reducing power consumption during bit line charging and discharging, especially for a wide range of macro sizes and aspect ratios, which affects overall active power consumption and read static noise margin.
Innovation Solution
Implementing a charge-sharing scheme to pre-charge bit lines to a voltage level less than the memory cell's high voltage level by sharing charge from the high voltage supply line capacitance with the bit line capacitance, using switches to control the charge transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If bit lines are charged to full voltage level using conventional charging methods, then the bit line voltage reaches the required level for reliable memory operation, but power consumption increases due to charging large capacitance to full voltage
Solution Approach 1:
The patent applies preliminary action by pre-charging the bit lines to a voltage level less than the memory cell's high voltage level before the actual read operation. This is achieved by sharing charge from the high voltage supply line capacitance with the bit line capacitance through controlled switching. The bit lines are prepared in advance at a reduced voltage level, which reduces the energy required for charging while maintaining reliable operation through the subsequent read process.
Solution Approach 2:
The patent changes the voltage parameter of the bit line pre-charge from the conventional full voltage level (VDD) to a reduced voltage level (less than VDD). This parameter change is achieved by controlling the charge sharing process between the high voltage supply line capacitance and the bit line capacitance. By operating at this reduced voltage level during pre-charge, the energy consumption is reduced while the read operation can still proceed reliably.
2Ease of manufacture
If conventional charging methods are used, then the charging process is simple to implement, but the method does not scale effectively across various macro sizes and aspect ratios
Solution Approach 1:
The patent achieves universality by creating a charge-sharing pre-charge scheme that can be applied across different SRAM architectures, macro sizes, and aspect ratios. The method uses the existing high voltage supply line capacitance and bit line capacitance in a charge-sharing arrangement controlled by switches, which is a universal approach that works regardless of the specific memory array dimensions or configuration. This makes the solution adaptable and scalable while maintaining implementation feasibility.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method reduces SRAM active power consumption and improves read static noise margin by using a lower pre-charge voltage, which is scalable and applicable to various SRAM architectures.
Implementation Method 1
sharing charge from the high voltage supply line capacitance with the bit line capacitance
Data Source
AI summary
In one embodiment, a static random access memory (SRAM) device is provided. The SRAM device includes a memory cell, a bit line couple to the memory cell, a voltage supply line coupled to the memory cell, a control circuitry. The control circuitry is configured to charge a voltage supply line while the voltage supply line is electrically isolated from a bit line. A portion of the charge is transferred from the voltage supply line to the bit line. The voltage supply line is recharged while the voltage supply line is electrically isolated from the bit line storing the transferred portion of the charge. The memory cell is accessed using the recharge on the voltage supply line.