SRAM Bit Line Read Circuit for In-Memory Compute Accuracy
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Solution Overview
Problem
Variation in read current during simultaneous access of multiple rows in an SRAM array affects measurement accuracy in in-memory compute operations.
Innovation Solution
Implement a read circuit with first and second voltage sensing circuits and a processing circuit that average sense signals from complementary bit lines to account for read current variation, and a testing circuit to identify the less variable bit line for use in the read operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple rows are simultaneously accessed in an SRAM array for in-memory compute operation, then computation throughput is improved, but read current variation increases affecting measurement accuracy
Solution Approach 1:
The patent implements a feedback mechanism where the sensed voltages from complementary bit lines are fed back through the processing circuit which computes the difference between them. This feedback approach allows the system to automatically compensate for read current variations by using the complementary nature of the bit lines, thereby maintaining measurement precision while enabling simultaneous multi-row access for high throughput computation
Solution Approach 2:
The processing circuit acts as an intermediary between the voltage sensing circuits and the final computation output. It mediates the read current variation effect by computing the difference between complementary bit line voltages, which cancels out common-mode noise and current variations. This intermediary processing enables accurate measurements even during simultaneous multi-row access operations
2Measurement precision
If read current variation is compensated by averaging sense signals from complementary bit lines, then read accuracy is improved, but circuit complexity increases
Solution Approach 1:
The patent merges the functions of voltage sensing and differential computation into an integrated processing circuit. By combining the voltage sensing circuits with the differential computation logic, the design achieves read accuracy improvement through signal averaging while minimizing additional circuit complexity. The merged architecture processes complementary bit line signals together, extracting the desired computation result while naturally compensating for read current variations
Data Source
AI summary
An in-memory computation circuit includes a memory array with SRAM cells connected in rows by word lines and in columns by bit lines. A row controller circuit simultaneously actuates word lines in parallel for an in-memory compute operation. A column processing circuit includes a read circuit that operates to reduce sensitivity to variation in bit line read current. Additionally, a testing circuit senses analog signals on the complementary bit lines to identify one of the complementary bit lines as having a less variable read current. That identified one of the complementary bit lines is coupled to the read circuit for the in-memory compute operation.