SRAM Read Bit Line Precharge for Lower Read Power
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Solution Overview
Problem
Static random access memory (SRAM) units experience high power consumption due to frequent read/write operations, limiting processing speed, especially in applications like neural networks where read operations outnumber write operations.
Innovation Solution
The SRAM unit adjusts its working structure based on the quantity of data stored in each column by precharging or pre-discharging the read bit line accordingly, using a read circuit with transistors and control signals to minimize energy consumption during read operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the read bit line is precharged to a high level for every read operation, then the read operation can be performed reliably, but power consumption increases due to frequent charging operations
Solution Approach 1:
The patent changes the parameter of bit line precharge state from a fixed high level to a dynamic state that can be either high level or low level based on the stored data distribution. When most cells store logic 1, the bit line is precharged to high level; when most cells store logic 0, it is precharged to low level. This parameter change reduces unnecessary charging operations and lowers power consumption while maintaining read reliability.
Solution Approach 2:
The patent introduces dynamic adaptability to the static precharge operation by making the precharge state dependent on the data distribution in the storage array. The system dynamically determines the optimal precharge state (high or low) based on the proportion of logic 1s and 0s stored in the cells, transforming a static operation into a dynamic one that adapts to data patterns, thereby reducing power consumption without compromising reliability.
2Productivity
If the read bit line is always precharged to high level, then reading logic 0 data is efficient, but reading logic 1 data becomes inefficient as no charging is needed
Solution Approach 1:
The patent enables the system to serve itself by automatically determining the appropriate precharge state based on the data already stored in the array. The read circuitry detects the data distribution pattern and self-adjusts the bit line precharge state accordingly, eliminating the need for external control signals or complex additional circuitry. This self-service mechanism optimizes energy efficiency by matching the precharge state to the actual data content.
Solution Approach 2:
The patent implements a feedback mechanism where the data distribution information from the storage cells is used to control the precharge operation. The system monitors the proportion of logic 1s and 0s in the stored data and uses this feedback information to determine whether to precharge the bit line to high or low level, creating a closed-loop control system that optimizes energy efficiency based on actual operating conditions.
Data Source
AI summary
A static random access memory SRAM unit and a related apparatus are provided, to reduce power consumption of an SRAM when the SRAM memory is accessed. The SRAM unit is located in an SRAM memory, and the SRAM memory includes an SRAM storage array including a plurality of SRAM units. The SRAM unit includes: a storage circuit, connected to each of a write circuit and a read circuit, and configured to store data; the write circuit, configured to write data into the storage circuit; and the read circuit, configured to: after a read enabling signal is valid, enable data on a read bit line connected to the SRAM unit to be the data stored in the storage circuit.