SRAM BLC Driver Circuit for High-Speed Write Operations
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Solution Overview
Problem
Conventional SRAM memory systems experience reduced writing speed, particularly at higher clock frequencies and larger memory sizes, due to the voltage drop in complementary bit lines during logic zero writes, which affects the efficiency of data storage.
Innovation Solution
The introduction of a BLC driver circuit that produces a separate drive signal to maintain the BLC at a logic high level during logic low writes, preventing voltage drops and enhancing writing speed by using an inverter circuit and final stage circuit to ensure the BLC line reaches a logic high level.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional SRAM memory systems are used, then the basic memory storage function is achieved, but the writing speed is reduced due to voltage drop in complementary bit lines during logic zero writes
Solution Approach 1:
The write driver circuit is segmented into separate BLC driver and BLT driver circuits. The BLC driver is specifically designed to maintain the complementary bit line at a logic high level during logic zero writes, preventing voltage drops. This segmentation allows independent optimization of each bit line's driving characteristics, resolving the contradiction between writing speed and voltage stability.
Solution Approach 2:
Different driving characteristics are applied to different bit lines based on their specific requirements. The BLC driver provides strong driving capability to maintain high voltage levels during logic zero writes, while the BLT driver handles the true bit line differently. This local quality approach allows each bit line to operate under optimal conditions, improving overall writing speed while maintaining voltage stability.
2Productivity
If clock frequency is increased to improve performance, then processing speed increases, but writing speed in SRAM is reduced due to larger memory sizes and higher frequency effects
Solution Approach 1:
The BLC driver circuit performs preliminary action by maintaining the complementary bit line at a logic high level before and during the write operation. This preliminary maintenance of voltage levels prevents voltage drops that would otherwise occur during high-frequency write operations, enabling faster clock frequencies without sacrificing write speed.
Solution Approach 2:
The invention changes the electrical parameters of the BLC line by introducing a dedicated driver circuit that maintains the voltage level at logic high during logic zero writes. This parameter change (maintaining high voltage instead of allowing voltage drop) enables the SRAM to operate at higher clock frequencies while maintaining fast write speeds.
3Ease of operation
If conventional evaluation circuitry is used, then the basic read and write functions are achieved, but the BLC voltage drops below Vdd during read and write operations, reducing write speed
Solution Approach 1:
The BLC driving function is extracted from the conventional write driver circuit and separated into a dedicated BLC driver circuit. This extraction allows the BLC line to be independently controlled to maintain logic high levels during logic zero writes, eliminating the voltage drop problem while preserving basic read and write functionality through the conventional evaluation circuitry.
Data Source
AI summary
Methods and apparatus provide for writing data into and reading data from an anti-parallel storage circuit of an SRAM memory cell via a true bit line (BLT) and a complementary bit line (BLC); and preventing the complementary bit line (BLC) from substantially dropping from a pre-charge, logic high voltage level during operations in which a logic low level is written into the anti-parallel storage circuit.