SRAM Buffer Segmentation for CNN Memory Access
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Solution Overview
Problem
In convolutional neural networks (CNNs), the varying convolution kernel sizes across layers complicate memory addressing and reduce memory use efficiency when using multiple SRAMs as intermediate buffers, leading to increased processing time and complexity.
Innovation Solution
An operation processing apparatus and method that stores successive lines of the same feature plane in different memories and coordinates of multiple feature planes in the same layer in different memories, allowing simultaneous readout and write operations to improve memory access efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple SRAMs are used as intermediate buffers with varying convolution kernel sizes across layers, then the memory capacity is sufficient to store feature planes, but the memory addressing becomes complicated and memory use efficiency is reduced
Solution Approach 1:
The patent divides the intermediate buffer into multiple SRAMs and further segments the storage within each SRAM by separating line data into upper half and lower half. This segmentation allows independent access to different segments, simplifying the addressing scheme while maintaining sufficient storage capacity for feature planes with varying convolution kernel sizes.
Solution Approach 2:
The patent introduces an intermediary mechanism where line data is temporarily stored in a buffer and then distributed to multiple SRAMs based on address patterns. This intermediary approach mediates between the varying convolution kernel sizes and the fixed memory structure, reducing addressing complexity while preserving memory capacity.
2Quantity of substance
If multiple SRAMs are used as intermediate buffers, then memory storage is adequate, but the number of read cycles increases and processing time is extended
Solution Approach 1:
The patent performs preliminary organization of line data into upper and lower halves before storing in SRAMs. This preliminary action ensures that when convolution operations need to access feature planes, the data is already positioned for efficient retrieval, reducing the number of read cycles required and decreasing processing time despite using multiple SRAMs.
Solution Approach 2:
The patent enables continuous data flow by organizing memory storage so that successive lines of the same feature plane are stored in different memories, allowing simultaneous readout. This continuity eliminates idle time between read operations and maintains steady processing throughput, reducing overall processing time.
3Device complexity
If successive lines of the same feature plane are stored in the same memory, then memory structure is simple, but simultaneous readout is limited and access efficiency is reduced
Solution Approach 1:
The patent segments line data into upper and lower halves and distributes them to different SRAMs. This segmentation enables simultaneous readout from multiple memories, dramatically increasing data retrieval speed while maintaining a relatively simple memory structure through systematic organization.
Solution Approach 2:
The patent transitions from a single-dimension storage approach (storing all lines of a feature plane in one memory) to a two-dimension approach (distributing lines across multiple memories with upper/lower half separation). This dimensional change enables parallel access paths, improving productivity without significantly increasing structural complexity.
4Device complexity
If data is read out sequentially from a single memory, then addressing is simple, but the number of read cycles increases and processing speed decreases
Solution Approach 1:
The patent segments feature plane data across multiple SRAMs with clear addressing patterns for upper and lower halves. This segmentation enables parallel readout operations while maintaining simple addressing schemes through systematic address allocation, thereby increasing data retrieval speed without significantly complicating the addressing mechanism.
Solution Approach 2:
The patent merges the readout operations from multiple SRAMs into a unified data flow for convolution operations. By combining the simultaneous readout capability of multiple memories with a unified addressing scheme, the system achieves high-speed data retrieval while keeping the addressing logic relatively simple through coordinated access patterns.
Data Source
AI summary
An apparatus for calculating feature planes by hierarchically performing filter operation processing for input image data, comprises an operation unit configured to perform a convolution operation, a holding unit including memories configured to store image data and an operation result of the operation unit, a unit configured to receive the operation result, and write, out of the operation result, data of successive lines of the same feature plane in different memories of the memories and write data at the same coordinates of feature planes in the same layer in different memories of the memories, and a unit configured to read out the data of the successive lines from the different memories, read out the data at the same coordinates of the different feature planes in the same layer, and transmit the data to the operation unit.