SRAM Buffer Synchronization for Non-Volatile Memory Access
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Solution Overview
Problem
Conventional memory systems face challenges in providing synchronous access to non-volatile memory due to longer response times, which hinder efficient data access on synchronous buses like DDR4, leading to increased access times for hosts.
Innovation Solution
The implementation of a synchronization component and an SRAM buffer that moves data between non-volatile memory and DRAM using reserved refresh cycles, allowing synchronous memory bus access by synchronizing data transfers and maintaining a mapping table for efficient access, effectively matching the timing requirements of DRAM.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If non-volatile memory is accessed directly on a synchronous memory bus, then storage capacity and data retention are improved, but access time and response time increase
Solution Approach 1:
The patent introduces an SRAM buffer as an intermediary component between the non-volatile memory and the synchronous memory bus. The SRAM buffer temporarily stores data being transferred, allowing the host to access non-volatile memory through the buffer at synchronous speeds while the actual non-volatile memory operations can proceed at their native, slower speeds. This mediator resolves the timing mismatch between fast synchronous bus operations and slow non-volatile memory operations.
Solution Approach 2:
The system performs preliminary data transfer operations by moving data from non-volatile memory to the SRAM buffer in advance of when the host needs to access it. The buffer is pre-loaded with data during idle periods or using reserved refresh cycles, so that when the host initiates an access operation, the data is already available in the fast buffer, eliminating access delays.
2Speed
If data transfer between non-volatile memory and DRAM is performed, then access speed is improved, but timing synchronization becomes more complex
Solution Approach 1:
The patent utilizes periodic DRAM refresh cycles as structured time windows for data transfer operations. By reserving specific refresh cycles for buffer-to-memory transfers and host-to-buffer transfers, the system creates a periodic rhythm to data movements. This periodic scheduling simplifies timing synchronization compared to arbitrary transfers, as all operations are aligned to the regular refresh cycle boundaries.
Solution Approach 2:
The system maintains continuous useful action by overlapping operations: while the host transfers data to the buffer during allocated cycles, the buffer simultaneously performs transfers to/from non-volatile memory during reserved refresh cycles. This continuous parallel operation maximizes throughput and keeps the data path busy, improving effective access speed while managing timing complexity through structured scheduling.
Data Source
AI summary
A computing system having memory components, including first memory and second memory, wherein the first memory is available to a host system for read and write access over a memory bus during one or more of a first plurality of windows. The computing system further includes a processing device, operatively coupled with the memory components, to: receive, from a driver of the host system, a request regarding a page of data stored in the second memory; responsive to the request, transfer the page from the second memory to a buffer; and write the page from the buffer to the first memory, wherein the page is written to the first memory during at least one of a second plurality of windows corresponding to a refresh timing for the memory bus, and the refresh timing is controlled at the host system.