SRAM Buffered-Read Bit Cell Testing via Direct Access
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Solution Overview
Problem
The challenge in semiconductor integrated circuit processing is the difficulty in accurately diagnosing subtle defects in high-density memory cells without the time-consuming and destructive physical failure analysis, especially with complex SRAM cells like the 8T SRAM, which complicates characterization and defect identification.
Innovation Solution
A circuit and method for testing and characterizing individual transistors and bit cells in a static random access memory (SRAM) using direct bit line access (DBLA) to measure current and voltage characteristics, allowing for non-destructive and efficient diagnosis of memory cell defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If physical failure analysis (PFA) is used to diagnose subtle defects in high-density memory cells, then measurement precision is improved, but loss of time and productivity deteriorate
Solution Approach 1:
The patent replaces the mechanical/physical failure analysis process with an electrical testing method. The test circuit applies voltage to bit lines and word lines, measures current through transistors, and diagnoses defects electrically rather than through physical inspection, thereby eliminating time-consuming PFA while maintaining diagnostic accuracy
Solution Approach 2:
The patent introduces a test circuit as an intermediary between the memory cell and the diagnosis system. This test circuit includes test bit lines and test word lines that interface with the memory cell transistors, enabling indirect measurement of transistor characteristics without direct physical intervention in the memory cell structure
2Measurement precision
If physical failure analysis (PFA) is used to determine defect causes, then measurement precision is improved, but device complexity increases due to destructive nature
Solution Approach 1:
The patent replaces destructive physical failure analysis with non-destructive electrical characterization. By measuring current-voltage characteristics through the test circuit, the method identifies defect causes (such as transistor threshold voltage shifts or leakage) without physically damaging the device, simplifying the analysis process
Solution Approach 2:
The patent creates an electrical model/copy of the memory cell's normal operation through the test circuit. By replicating the transistor switching and current flow paths electrically, the test circuit allows diagnosis of defect causes by comparing measured characteristics against expected behavior, avoiding complex physical dissection
3Productivity
If complex 8T SRAM memory cells are used to increase packing density, then productivity is improved, but device complexity increases making characterization difficult
Solution Approach 1:
The patent segments the 8T SRAM memory cell into individual transistor components for testing. The test circuit independently tests each transistor (T1-T8) by applying voltages to specific bit lines and word lines while measuring currents through individual transistors, breaking down the complex cell structure into manageable test units
Solution Approach 2:
The patent applies local quality testing by characterizing each transistor's specific electrical properties (threshold voltage, leakage current, on-current) independently within the 8T cell context. The test circuit provides localized voltage application and current measurement for each transistor, enabling precise identification of which specific transistor component has a defect
4Productivity
If minimum feature sizes are reduced to increase packing density, then productivity is improved, but manufacturing precision requirements increase making defect diagnosis harder
Solution Approach 1:
The patent replaces physical inspection methods with electrical measurement to diagnose defects in minimum-size transistors. By measuring current characteristics through the test circuit, the method can detect subtle manufacturing variations (such as threshold voltage shifts from dielectric defects) that are invisible to physical inspection, maintaining diagnostic capability at reduced feature sizes
Data Source
AI summary
An SRAM with buffered-read bit cells is disclosed (FIGS. 1-6). The integrated circuit includes a plurality of memory cells (102). Each memory cell has a plurality of transistors (200,202). A first memory cell (FIG. 2) is arranged to store a data signal in response to an active write word line (WWL) and to produce the data signal in response to an active read word line (RWL). A test circuit (104) formed on the integrated circuit is operable to test current and voltage characteristics of each transistor of the plurality of transistors of the first memory cell (FIGS. 7-10).