2-Port SRAM Cell Buried Interconnect Layout for Speed Optimization
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Solution Overview
Problem
There is a lack of specific studies on the layout structure of 2-port SRAM cells with bit lines provided in the buried interconnect layer, which hinders the optimization of semiconductor storage device performance in terms of speed and write characteristics.
Innovation Solution
The layout structure of a 2-port SRAM cell is designed with write-bit lines and read-bit lines formed in the buried interconnect layer, while the write-word and read-word lines are formed in a layer above, allowing for increased film thickness of the buried interconnects to reduce resistance and improve operational speed and write characteristics without increasing the area of the semiconductor storage device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the film thickness of buried interconnects is increased to reduce resistance and improve speed, then the operational speed and write characteristics are improved, but the device area would increase
Solution Approach 1:
The patent applies dimensionality change by transitioning from planar interconnect layout to three-dimensional stacked interconnect layers. The write-bit lines are routed through the buried interconnect layer (lower layer) while word lines and read-bit lines are routed through the upper interconnect layer, allowing vertical separation of signal paths. This enables increased interconnect thickness in the buried layer without increasing lateral device area, as the additional interconnect capacity is achieved in the vertical dimension rather than by lateral expansion.
2Reliability
If the interconnect widths are increased to reduce resistance, then the write characteristics are improved, but the layout density decreases
Solution Approach 1:
The patent segments the interconnect system into multiple functional layers: the buried interconnect layer dedicated to write-bit lines, and the upper interconnect layer for word lines and read-bit lines. This segmentation allows each layer to be optimized independently - the buried layer can have wider, lower-resistance interconnects for write operations without compromising the density requirements of the upper layer, which handles read operations and control signals.
Solution Approach 2:
By moving write-bit lines to the buried interconnect layer below the transistor plane, the patent creates vertical separation between write and read pathways. This dimensional reorganization allows write-bit line interconnects to be widened for reduced resistance without increasing lateral footprint, as the width increase is accommodated in the lower layer without interfering with the upper layer's dense transistor and interconnect layout.
3Speed
If write-bit lines are provided in the buried interconnect layer, then the resistance is reduced and speed is improved, but the layout structure becomes more complex
Solution Approach 1:
The buried interconnect layer serves multiple functions: it provides low-resistance write-bit line pathways for fast write operations, and simultaneously acts as a structural foundation that supports the upper interconnect layer. The dual-function design reduces overall device complexity by eliminating the need for separate dedicated low-resistance pathways, as the buried interconnect layer fulfills both structural and high-speed signal transmission roles.
Data Source
AI summary
A 2-port SRAM cell includes load transistors, drive transistors, access transistors, a read drive transistor, and a read access transistor. Buried interconnects corresponding to write-bit lines, respectively are formed in a buried interconnect layer so as to extend in a first direction. Interconnects corresponding to a read-word line and a write-word line, respectively are formed in an interconnect layer above the buried interconnect layer so as to extend in a second direction.