SRAM Buried Layer Patterns for Silicide Isolation

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Solution Overview

Problem

The existing silicide process in SRAM devices faces challenges due to structural limitations, particularly in the peripheral circuit region, where metal contamination from the silicide process can degrade the electrical characteristics of the device, and the double polysilicon process is lengthy and costly.

Innovation Solution

The solution involves forming metal silicide layers on peripheral gate patterns and the semiconductor substrate, with buried layer patterns and protective interlayer-insulating layers to isolate and protect the cell gate patterns, allowing for a silicide process that prevents metal contamination and enhances device performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a silicide process is performed on peripheral gate patterns and semiconductor substrate near peripheral gate patterns, then electrical characteristics of peripheral circuits are improved, but metal contamination occurs in cell gate patterns which degrades electrical characteristics of SRAM device

Engineering Contradiction:

Improveelectrical characteristics of peripheral circuitsVSAvoidmetal contamination in cell gate patterns

Core Design Contradiction:

ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent divides the gate patterns into two distinct types: cell gate patterns (vertically stacked in cell array region) and peripheral gate patterns (laterally disposed in peripheral circuit region). This segmentation allows different processing approaches to be applied to each type, enabling silicide process on peripheral gates while protecting cell gates from metal contamination through spatial and structural separation.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent introduces an etch stop layer positioned between the cell gate patterns and the peripheral gate patterns/substrate. This etch stop layer acts as an intermediary barrier that prevents metal silicide formation in the cell gate region while allowing silicide process to proceed on the peripheral gate patterns, thus protecting cell gates from metal contamination.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Adaptability or versatility

If double polysilicon process is used to provide both logic and memory circuits in a single chip, then device functionality is improved, but fabrication process becomes lengthy and cost increases

Engineering Contradiction:

Improvedevice functionalityVSAvoidfabrication process efficiency

Core Design Contradiction:

Adaptability or versatilityVSProductivity

Solution Approach 1:

The patent merges the formation of cell gate patterns and peripheral gate patterns into a single simultaneous fabrication process. By using a unified gate pattern formation approach that accommodates both vertically stacked cell gates and laterally disposed peripheral gates, the patent eliminates the need for separate double polysilicon processes, thereby reducing fabrication steps and cost while maintaining the ability to provide both logic and memory circuits on a single chip.

Inventive Principle:

Principle #5Merging (Combining)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach effectively prevents metal contamination, improves the electrical characteristics of SRAM devices, and reduces the complexity and cost of the fabrication process by allowing simultaneous processing of memory and logic circuits.

Implementation Method 1

Metal silicide layers are disposed on at least one portion of the peripheral gate patterns and on portions of the semiconductor substrate near the peripheral gate patterns

Methodology Applied

Scientific EffectSilicide process: Chemical Bonding

Implementation Method 2

an etch stop layer and a protective interlayer-insulating layer are disposed around the peripheral gate patterns and on the cell array region

Methodology Applied

Scientific EffectPhysical barrier protection: Physical Containment

Implementation Method 3

buried layer patterns are disposed on the peripheral gate patterns and on at least a portion of the metal silicide layers and the portions of the semiconductor substrate near the peripheral gate patterns

Methodology Applied

Scientific EffectLayer deposition: Deposition (physical)

Data Source

PatentUS8048727B2Methods of forming SRAM devices having buried layer patterns

Publication Date: 2011.11.01 SAMSUNG ELECTRONICS CO LTD

AI summary

An SRAM device includes a substrate having at least one cell active region in a cell array region and a plurality of peripheral active regions in a peripheral circuit region, a plurality of stacked cell gate patterns in the cell array region, and a plurality of peripheral gate patterns disposed on the peripheral active regions in the peripheral circuit region. Metal silicide layers are disposed on at least one portion of the peripheral gate patterns and on the semiconductor substrate near the peripheral gate patterns, and buried layer patterns are disposed on the peripheral gate patterns and on at least a portion of the metal silicide layers and the portions of the semiconductor substrate near the peripheral gate patterns. An etch stop layer and a protective interlayer-insulating layer are disposed around the peripheral gate patterns and on the cell array region. Methods of forming an SRAM device are also disclosed.