2-Port SRAM Layout Using Buried Global Read-Bit Lines
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Solution Overview
Problem
There is no specific study on the layout of a 2-port SRAM cell with bit lines provided in the buried interconnect layer, which is necessary for high integration of semiconductor integrated circuits.
Innovation Solution
A semiconductor storage device is designed with multiple memory arrays, each containing 2-port SRAM cells connected to write-bit lines, local read-bit lines, and global read-bit lines. The global read-bit lines are formed in a buried interconnect layer, eliminating the need for interconnects in the upper interconnect layer, and allowing for reduced area and increased film thickness to lower resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the global read-bit line is formed in the interconnect layer above the buried interconnect layer, then the layout is simpler, but the area of the semiconductor storage device increases
Solution Approach 1:
The patent applies dimensionality change by moving the global read-bit line from the upper interconnect layer to the buried interconnect layer beneath the transistor substrate. This spatial reconfiguration allows the bit line to extend underneath the transistor array without occupying additional lateral area, effectively utilizing the vertical dimension to resolve the area expansion problem while maintaining layout simplicity.
2Reliability
If the film thickness of the buried interconnect is increased, then the resistance of the global read-bit line decreases, but the manufacturing process becomes more complex
Solution Approach 1:
The patent applies parameter changes by increasing the film thickness of the buried interconnect from conventional dimensions to approximately 50 nm or more. This parameter modification directly reduces the electrical resistance of the global read-bit line, improving signal transmission reliability and enabling high-speed operation, while the increased thickness is achieved through standard thin-film deposition processes.
3Ease of operation
If more global read-bit lines are provided, then each SRAM cell has better access, but the device area and complexity increase
Solution Approach 1:
The patent applies universality by designing a single global read-bit line that serves multiple SRAM cells simultaneously. The buried interconnect layer enables this line to extend underneath the transistor array, allowing one bit line to provide read access to numerous cells across the memory array, thereby eliminating the need for separate bit lines for each cell and reducing overall device area and complexity.
Data Source
AI summary
Multiple SRAM cells are commonly connected to write-bit lines extending in a Y-direction and a local read-bit line extending in the Y-direction. A local amplifier connected to the local read-bit line outputs a signal received from a selected SRAM cell through the local read-bit line to the global read-bit line. A buried interconnect corresponding to the global read-bit line is formed in a buried interconnect layer. An interconnect corresponding to the local read-bit line is formed in a first interconnect layer.