SRAM Burst Mode Operation Reduces Power via Bit Line Pre-Charge
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Solution Overview
Problem
Conventional static random-access memory (SRAM) requires high-gain sense amplifiers to detect small voltage differences during read operations, leading to power inefficiency and increased die space, which hinders memory density and power efficiency.
Innovation Solution
Implementing a burst-mode operation with column multiplexing and charge-transfer transistors that amplify bit line voltage differences across sense nodes, allowing for the use of low-power reset-set latches and reducing the need for high-gain sense amplifiers, while maintaining memory density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional SRAM uses high-gain sense amplifiers to detect small voltage differences, then measurement precision is improved, but power consumption increases and device complexity increases
Solution Approach 1:
The patent pre-charges bit lines to the power supply voltage before read operations, creating a prepared state that amplifies the voltage difference during sensing. This preliminary action eliminates the need for high-gain sense amplifiers by ensuring maximum voltage swing is available at the sense nodes, thereby reducing power consumption while maintaining detection precision
Solution Approach 2:
The patent changes the voltage parameter of bit lines from conventional levels to full rail voltage (power supply voltage) during pre-charge. This parameter change creates larger voltage differences during read operations, allowing simple sense amplifiers to achieve sufficient measurement precision without requiring high gain, thus reducing power consumption
2Measurement precision
If conventional SRAM uses high-gain sense amplifiers to detect small voltage differences, then measurement precision is improved, but device complexity and die space increase
Solution Approach 1:
By pre-charging bit lines to full power supply voltage before read operations, the patent prepares the circuit in advance to generate maximum voltage swing during sensing. This eliminates the need for complex high-gain sense amplifiers, allowing the use of simpler sense amplifier designs that occupy less die space and reduce overall device complexity
Solution Approach 2:
The patent modifies the voltage parameter of bit lines to full rail voltage during pre-charge, creating larger voltage differences that can be detected by simpler sense amplifiers. This parameter change enables the replacement of complex high-gain amplifiers with simpler circuits, thereby reducing device complexity and die space requirements
3Use of energy by moving object
If burst-mode operation reduces word line voltage assertion, then power consumption is reduced, but measurement precision may be affected
Solution Approach 1:
The patent pre-charges bit lines to full power supply voltage before burst-mode read operations. This preliminary action ensures that even when word line voltage assertion is reduced during burst mode, the pre-charged bit lines maintain sufficient voltage swing for accurate bit detection, thereby preserving measurement precision while reducing power consumption
Solution Approach 2:
The patent maintains the pre-charged state of bit lines throughout burst-mode operations, allowing continuous read operations without full re-charging cycles. This continuity enables reduced word line voltage assertion during subsequent reads in the burst sequence, achieving power reduction while maintaining detection accuracy through the sustained voltage difference
Data Source
AI summary
A memory is provided that is configured to practice both a conventional normal read operation and also a burst mode read operation. During the normal read operation, the memory pre-charges the bit lines in a group of multiplexed columns. Each column has a sense amplifier that latches a bit decision for the column during the normal read operation. If a subsequent read operation addresses the same group of multiplexed columns, the memory invokes the burst-mode read operation during which the bit lines are not pre-charged.