SRAM Burst Read Write Energy Dissipation Optimization
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Solution Overview
Problem
Conventional SRAM designs, such as the 6T SRAM, are inefficient in terms of energy dissipation due to their random access pattern, particularly in applications like deep neural networks, where memory read contributes significant dynamic capacitance, limiting performance and increasing power consumption.
Innovation Solution
The proposed solution optimizes SRAM architecture by leveraging prior knowledge of access patterns to implement burst read and write operations, reducing energy dissipation by pre-charging and reading/writing multiple bit-cells with a single bit-line pre-charge and word-line pulse, thereby minimizing unnecessary capacitance switching and toggling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If conventional 6T SRAM is designed for random access pattern, then it can handle general memory operations, but it dissipates significant energy due to unnecessary bit-line pre-charge and word-line pulse operations
Solution Approach 1:
The patent applies preliminary action by pre-charging bit-lines and maintaining word-line pulses across multiple consecutive cycles before actual memory access. This allows the memory array to be ready for burst operations, reducing the need for repeated pre-charge and pulse operations during sequential access patterns typical in deep neural network operations
Solution Approach 2:
The patent implements periodic action through burst read/write operations that access multiple memory locations sequentially within a single pre-charge cycle. This periodic access pattern matches the temporal locality of deep neural network weight accesses, reducing energy dissipation by eliminating redundant pre-charge and word-line pulse operations between consecutive accesses
2Reliability
If memory read operations are performed with individual bit-line pre-charge for each access, then data can be read accurately, but dynamic capacitance increases significantly
Solution Approach 1:
The patent merges multiple bit-line pre-charge operations into a single pre-charge cycle that spans several consecutive memory access cycles. This combining of pre-charge operations maintains data read accuracy while significantly reducing the total dynamic capacitance associated with repeated bit-line charging and discharging operations
3Reliability
If conventional SRAM performs separate pre-charge and write operations for each memory location, then write accuracy is maintained, but write energy consumption increases
Solution Approach 1:
The patent applies preliminary action by pre-charging bit-lines before a series of consecutive write operations. This preliminary pre-charge maintains write accuracy by ensuring proper voltage levels are established, while reducing write energy consumption by eliminating the need to re-pre-charge bit-lines for each subsequent write operation in the burst sequence
Data Source
AI summary
Prior knowledge of access pattern is leveraged to improve energy dissipation for general matrix operations. This improves memory access energy for a multitude of applications such as image processing, deep neural networks, and scientific computing workloads, for example. In some embodiments, prior knowledge of access pattern allows for burst read and/or write operations. As such, burst mode solution can provide energy savings in both READ (RD) and WRITE (WR) operations. For machine learning or inference, the weight values are known ahead in time (e.g., inference operation), and so the unused bytes in the cache line are exploited to store a sparsity map that is used for disabling read from either upper or lower half of the cache line, thus saving dynamic capacitance.